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1. 发明申请

US20060105510A1 Transistor or semiconductor device and method of fabricating the same 有权
标题翻译：晶体管或半导体器件及其制造方法
公开(公告)号：US20060105510A1
公开(公告)日：2006-05-18
申请号：US11179971
申请日：2005-07-11
申请人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
发明人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

2. 发明申请

US20070238232A9 Transistor or semiconductor device and method of fabricating the same 有权
标题翻译：晶体管或半导体器件及其制造方法
公开(公告)号：US20070238232A9
公开(公告)日：2007-10-11
申请号：US11179971
申请日：2005-07-12
申请人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
发明人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

3. 发明申请

US20060121658A1 Method of manufacturing field effect transistor 有权
标题翻译：制造场效应晶体管的方法
公开(公告)号：US20060121658A1
公开(公告)日：2006-06-08
申请号：US11180726
申请日：2005-07-14
申请人： Ho Ahn , Jong Lim , Hong Ji , Woo Chang , Jae Mun , Hae Kim
发明人： Ho Ahn , Jong Lim , Hong Ji , Woo Chang , Jae Mun , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66856 , H01L29/66462
摘要： Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.
摘要翻译：提供了制造场效应晶体管（FET）的方法。该方法包括以下步骤：在源极和漏极区域的衬底上形成欧姆金属层; 在所得结构的整个表面上顺序地形成绝缘层和多层抗蚀剂层，并且同时形成除了欧姆金属层以外的第一区域和不包括欧姆金属层的第二区域中具有不同形状的抗蚀剂图案，其中最下面抗蚀剂图案在第一区域中暴露，并且绝缘层在第二区域中暴露; 通过分别使用抗蚀剂图案作为蚀刻掩模，同时蚀刻暴露的绝缘层和暴露的最下面的抗蚀剂图案来暴露衬底和绝缘层; 对曝光的衬底进行凹陷处理并蚀刻暴露的绝缘层以露出衬底; 以及在衬底上形成具有彼此不同蚀刻深度的栅极凹陷区域，沉积预定的栅极金属和去除抗蚀剂图案。在该方法中，可以使用最少数量的工艺来制造具有不同阈值电压的晶体管，而不需要额外的掩模图案，结果可以降低生产成本，并且可以提高半导体器件的稳定性和生产率。

4. 发明申请

US20070132514A1 Power device having connection structure compensating for reactance component of transmission line 失效
标题翻译：具有补偿传输线电抗分量的连接结构的功率器件
公开(公告)号：US20070132514A1
公开(公告)日：2007-06-14
申请号：US11519668
申请日：2006-09-12
申请人： Woo Chang , Jae Mun , Haecheon Kim , Jong Lim , Hong Ji , Ho Ahn
发明人： Woo Chang , Jae Mun , Haecheon Kim , Jong Lim , Hong Ji , Ho Ahn
IPC分类号： H03F3/68
CPC分类号： H03F3/602 , H03F3/211 , H03F2200/366 , H03F2200/447 , H03F2200/543 , H03F2203/21178
摘要： Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.
摘要翻译：提供了具有补偿电抗分量的连接结构的功率器件，其中配置并连接晶体管，以通过补偿导致由于用于连接多个元件的传输线引起的相位差的电抗分量来最小化由热引起的晶体管性质的劣化的晶体管并联，使得用于高频功率放大器的功率器件输出高功率，并将由高输出功率产生的热量传输到散热器。

5. 发明申请

US20070099368A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20070099368A1
公开(公告)日：2007-05-03
申请号：US11454721
申请日：2006-06-16
申请人： Ho Ahn , Jong Lim , Jae Mun , Hong Ji , Woo Chang , Hea Kim
发明人： Ho Ahn , Jong Lim , Jae Mun , Hong Ji , Woo Chang , Hea Kim
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L29/812 , H01L29/42316 , H01L29/66462 , H01L29/66856 , H01L29/778
摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.
摘要翻译：提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

6. 发明申请

US20060124963A1 Transistor of semiconductor device and method of fabricating the same 失效
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US20060124963A1
公开(公告)日：2006-06-15
申请号：US11280608
申请日：2005-11-15
申请人： Jae Mun , Hung Ji , Ho Ahn , Hae Kim
发明人： Jae Mun , Hung Ji , Ho Ahn , Hae Kim
IPC分类号： H01L29/739
CPC分类号： H01L29/7785 , H01L29/42316
摘要： Provided are a transistor of a semiconductor device and a method of fabricating the same. The transistor of a semiconductor device includes an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant concentration from the first Si planar doped layer, and a second conductive layer, which are sequentially formed on a semi-insulating substrate; a source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate the first Si planar doped layer to a predetermined depth to form an ohmic contact; and a gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode, the source electrode and the drain electrode are electrically insulated by an insulating layer, and a predetermined part of an upper part of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode. Therefore, a maximum voltage that can be applied to the switching device is increased due to increases of a gate turn-on voltage and a breakdown voltage, and decrease of a parallel conduction component. As a result of this improved power handling capability, high-power and low-distortion characteristics and high isolation can be expected from the switching device.
摘要翻译：提供半导体器件的晶体管及其制造方法。半导体器件的晶体管包括具有缓冲层，第一硅（Si）平面掺杂层，第一导电层，具有与第一Si平面掺杂层不同的掺杂剂浓度的第二Si平面掺杂层的外延衬底，以及第二导电层，其依次形成在半绝缘基板上; 源电极和漏电极，形成在第二导电层的两侧，以将第一Si平面掺杂层穿透到预定深度以形成欧姆接触; 以及形成在所述源电极和所述漏电极之间的所述第二导电层上的栅电极，以与所述第二导电层形成接触，其中所述栅电极，所述源电极和所述漏极由绝缘层电绝缘，栅电极的上部的预定部分形成为与源电极和漏电极中的至少一个重叠。因此，由于栅极导通电压和击穿电压的增加以及并联导通分量的降低，可以施加到开关器件的最大电压增加。由于这种改进的功率处理能力，可以期望从开关器件获得高功率和低失真特性以及高隔离度。

7. 发明申请

US20060208269A1 Side-emitting LED package having scattering area and backlight apparatus incorporating the LED lens 有权
标题翻译：具有散射面积的侧面发光LED封装和并入LED透镜的背光装置
公开(公告)号：US20060208269A1
公开(公告)日：2006-09-21
申请号：US11370021
申请日：2006-03-08
申请人： Bum Kim , Hyung Kim , Ho Ahn , Young Jeong , Sung Yang
发明人： Bum Kim , Hyung Kim , Ho Ahn , Young Jeong , Sung Yang
IPC分类号： H01L33/00
CPC分类号： H01L33/54 , G02F1/133603 , G02F1/133615 , H01L33/60 , H01L2933/0091
摘要： The invention provides an LED package and a backlight device incorporating the LED lens. The LED package has a bottom surface and a light exiting surface cylindrically extended around a central axis of the package from the bottom surface. Also, a reflecting surface is positioned on an opposite side of the bottom surface and symmetrical around the central axis such that light incident from the bottom surface is reflected toward the light exiting surface. Further, a scattering area is formed on the reflecting surface. According to the invention, by applying scattering materials on the reflecting surface of the LED package, a reflecting paper does not need to be attached, thereby simplifying a process and reducing the manufacture time and cost.
摘要翻译：本发明提供了一种LED封装和结合了LED透镜的背光装置。 LED封装具有底表面和从底表面围绕封装的中心轴线圆柱形延伸的光出射表面。此外，反射表面位于底表面的相对侧并且围绕中心轴对称，使得从底表面入射的光被反射到光出射表面。此外，在反射面上形成散射区域。根据本发明，通过在LED封装的反射面上施加散射材料，不需要附着反射纸，从而简化了工艺并缩短了制造时间和成本。

8. 发明申请

US20060034097A1 Light emitting diode lens and backlight apparatus having the same 有权
标题翻译：发光二极管透镜和具有相同的背光装置
公开(公告)号：US20060034097A1
公开(公告)日：2006-02-16
申请号：US10953816
申请日：2004-09-30
申请人： Hun Hahm , Jung Park , Young Jeong , Young Park , Hyung Kim , Ho Ahn
发明人： Hun Hahm , Jung Park , Young Jeong , Young Park , Hyung Kim , Ho Ahn
IPC分类号： F21V7/04
CPC分类号： H01L33/58 , H01L33/54 , H01L33/60
摘要： The present invention relates to an LED lens, in which a planar bottom has a pair of halves symmetrically connected with each other about a reference line and narrowed in the vicinity of the reference line. A pair of substantially semicircular reflecting surfaces are extended from both edges of the bottom connected with both ends of the reference line. A radiating surface is connected with remaining edges of the bottom and semicircular edges of the reflecting surfaces. The reflecting surfaces reflect light beams are introduced from the LED chip through the bottom toward the radiating surface. The radiating surface radiates the light beams to the outside when the light beams are introduced to the radiating surface through reflection from the reflecting surfaces and directly through the bottom, so that the light beams are radiated to the outside in a predetermined beam angle.
摘要翻译：本发明涉及一种LED透镜，其中平面底部具有围绕参考线彼此对称连接并在基准线附近变窄的一对半部。一对基本上半圆形的反射表面从与参考线的两端连接的底部的两个边缘延伸。辐射表面与反射表面的底部和半圆形边缘的剩余边缘连接。反射面反射光束从LED芯片通过底部朝向辐射表面引入。当光束通过反射表面反射而直接通过底部将光束引入辐射表面时，辐射表面将光束照射到外部，使得光束以预定的光束角度辐射到外部。

9. 发明申请

US20060169999A1 LED package frame and LED package having the same 有权
标题翻译： LED封装框架和LED封装相同
公开(公告)号：US20060169999A1
公开(公告)日：2006-08-03
申请号：US11319101
申请日：2005-12-28
申请人： Young Park , Seung Lee , Hun Hahm , Hyung Kim , Bum Kim , Young Jeong , Ho Ahn , Jung Park
发明人： Young Park , Seung Lee , Hun Hahm , Hyung Kim , Bum Kim , Young Jeong , Ho Ahn , Jung Park
IPC分类号： H01L33/00
CPC分类号： H01L33/62 , H01L33/60 , H01L33/642 , H01L33/647 , H01L2224/48091 , H01L2224/48247 , H01L2924/01079 , H01L2924/12041 , H01L2924/00014
摘要： The invention relates to an LED package frame and an LED package incorporating the same. The LED package frame comprises an LED chip; and a heat conductive member made of a lump of high heat conductivity material. The heat conductive member has a receiving part at a lateral portion, and is mounted with the LED chip. A lead is inserted at one end into the receiving part of the heat conductive member, and electrically connected to the LED chip. An electrically insulating layer is placed in tight contact between the lead and the receiving part of the heat conductive member to separate the lead from the receiving part. With the lead inserted into the heat conductive member, it is possible to reduce size while maintaining high heat conductivity and stability. Also, it is possible to provide an LED package frame and a high power LED package by fixing the lead fixed to the heat conductive member without a jig.
摘要翻译：本发明涉及一种LED封装框架和一个包含该LED封装框架的LED封装件。 LED封装框架包括LED芯片; 以及由高导热性材料块制成的导热构件。导热构件在侧部具有接收部，并且安装有LED芯片。引线一端插入导热部件的接收部分，并与LED芯片电连接。电绝缘层被放置在引导件和导热构件的接收部分之间的紧密接触中以将引线与接收部分分离。通过将导线插入导热构件，可以在保持高导热性和稳定性的同时减小尺寸。此外，通过将固定在导热构件上的引线固定而不用夹具，可以提供LED封装框架和大功率LED封装。

10. 发明申请

US20060284203A1 Side-emitting LED package and manufacturing method of the same 有权
标题翻译：侧面发光LED封装及其制造方法相同
公开(公告)号：US20060284203A1
公开(公告)日：2006-12-21
申请号：US11444397
申请日：2006-06-01
申请人： Kyung Han , Hun Hahm , Dae Kim , Ho Ahn , Seong Han , Young Park , Seon Lee
发明人： Kyung Han , Hun Hahm , Dae Kim , Ho Ahn , Seong Han , Young Park , Seon Lee
IPC分类号： H01L33/00
CPC分类号： H01L33/60 , H01L24/97 , H01L25/0753 , H01L33/0095 , H01L33/486 , H01L33/54 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/15787 , H01L2924/181 , H05K2201/10106 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to a side-emitting LED package and a manufacturing method of the same. The invention provides a side-emitting LED package for emitting light from a light source sideward including a substrate with an electrode formed thereon. The package also includes a light source disposed on the substrate, a molded part that covers and protects the substrate with the light source thereon, and a reflective layer that covers an outer surface of the molded part. The molded part with the reflective layer forms a light transmitting surface in one side thereof. The invention allows easy manufacture of a reflecting surface in a desired shape, miniaturization regardless of the LED chip size, mass-production in an LED array, significantly improving productivity.
摘要翻译：本发明涉及一种侧面发光LED封装及其制造方法。本发明提供一种用于从侧向发光的侧光发射LED封装件，其包括形成有电极的基板。封装还包括设置在基板上的光源，覆盖并保护其上具有光源的基板的模制部件和覆盖模制部件的外表面的反射层。具有反射层的模制部件在其一侧形成透光表面。本发明允许容易地制造所需形状的反射表面，而不管LED芯片尺寸如何，小型化，LED阵列中的批量生产，显着提高生产率。

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