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1. 发明申请

US20070099368A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20070099368A1
公开(公告)日：2007-05-03
申请号：US11454721
申请日：2006-06-16
申请人： Ho Ahn , Jong Lim , Jae Mun , Hong Ji , Woo Chang , Hea Kim
发明人： Ho Ahn , Jong Lim , Jae Mun , Hong Ji , Woo Chang , Hea Kim
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L29/812 , H01L29/42316 , H01L29/66462 , H01L29/66856 , H01L29/778
摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.
摘要翻译：提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

2. 发明申请

US20060121658A1 Method of manufacturing field effect transistor 有权
标题翻译：制造场效应晶体管的方法
公开(公告)号：US20060121658A1
公开(公告)日：2006-06-08
申请号：US11180726
申请日：2005-07-14
申请人： Ho Ahn , Jong Lim , Hong Ji , Woo Chang , Jae Mun , Hae Kim
发明人： Ho Ahn , Jong Lim , Hong Ji , Woo Chang , Jae Mun , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66856 , H01L29/66462
摘要： Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.
摘要翻译：提供了制造场效应晶体管（FET）的方法。该方法包括以下步骤：在源极和漏极区域的衬底上形成欧姆金属层; 在所得结构的整个表面上顺序地形成绝缘层和多层抗蚀剂层，并且同时形成除了欧姆金属层以外的第一区域和不包括欧姆金属层的第二区域中具有不同形状的抗蚀剂图案，其中最下面抗蚀剂图案在第一区域中暴露，并且绝缘层在第二区域中暴露; 通过分别使用抗蚀剂图案作为蚀刻掩模，同时蚀刻暴露的绝缘层和暴露的最下面的抗蚀剂图案来暴露衬底和绝缘层; 对曝光的衬底进行凹陷处理并蚀刻暴露的绝缘层以露出衬底; 以及在衬底上形成具有彼此不同蚀刻深度的栅极凹陷区域，沉积预定的栅极金属和去除抗蚀剂图案。在该方法中，可以使用最少数量的工艺来制造具有不同阈值电压的晶体管，而不需要额外的掩模图案，结果可以降低生产成本，并且可以提高半导体器件的稳定性和生产率。

3. 发明申请

US20070238232A9 Transistor or semiconductor device and method of fabricating the same 有权
标题翻译：晶体管或半导体器件及其制造方法
公开(公告)号：US20070238232A9
公开(公告)日：2007-10-11
申请号：US11179971
申请日：2005-07-12
申请人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
发明人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

4. 发明申请

US20060105510A1 Transistor or semiconductor device and method of fabricating the same 有权
标题翻译：晶体管或半导体器件及其制造方法
公开(公告)号：US20060105510A1
公开(公告)日：2006-05-18
申请号：US11179971
申请日：2005-07-11
申请人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
发明人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

5. 发明申请

US20070132514A1 Power device having connection structure compensating for reactance component of transmission line 失效
标题翻译：具有补偿传输线电抗分量的连接结构的功率器件
公开(公告)号：US20070132514A1
公开(公告)日：2007-06-14
申请号：US11519668
申请日：2006-09-12
申请人： Woo Chang , Jae Mun , Haecheon Kim , Jong Lim , Hong Ji , Ho Ahn
发明人： Woo Chang , Jae Mun , Haecheon Kim , Jong Lim , Hong Ji , Ho Ahn
IPC分类号： H03F3/68
CPC分类号： H03F3/602 , H03F3/211 , H03F2200/366 , H03F2200/447 , H03F2200/543 , H03F2203/21178
摘要： Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.
摘要翻译：提供了具有补偿电抗分量的连接结构的功率器件，其中配置并连接晶体管，以通过补偿导致由于用于连接多个元件的传输线引起的相位差的电抗分量来最小化由热引起的晶体管性质的劣化的晶体管并联，使得用于高频功率放大器的功率器件输出高功率，并将由高输出功率产生的热量传输到散热器。

6. 发明申请

US20050016194A1 Unit type air conditioner 失效
标题翻译：单元式空调
公开(公告)号：US20050016194A1
公开(公告)日：2005-01-27
申请号：US10714668
申请日：2003-11-18
申请人： Jung Park , Woo Chang
发明人： Jung Park , Woo Chang
IPC分类号： F24F1/02 , F24F13/20 , F25D23/12 , F25D17/06
CPC分类号： F24F13/20 , F24F1/027
摘要： Unit type air conditioner including a base plate forming a bottom part thereof, a barrier projected upward from a center part of the base plate, to divides the unit type air conditioner into an indoor part for mounting an indoor heat exchanger thereon and an outdoor part for mounting an outdoor heat exchanger thereon, a shroud for leading air drawn from an outdoor to the outdoor heat exchanger, the shroud dividing an inside of the outdoor part, exterior members including a cabinet surrounding opposite side parts and rear side part of he outdoor part, and a cover on the cabinet to form an upper exterior of the outdoor part, and a brace fastened to the barrier, the shroud, and the exterior members, for preventing relative positional change between the barrier, the shroud, and the external members, thereby fastening components rigidly, to enhance fastening strength.
摘要翻译：单元型空调机，包括形成底部的基板，从基板的中心部向上方突出的挡板，将该单元型空调机分割为室内热交换器的室内部，以及室外部件，在室外安装室外热交换器，用于将从室外引导到室外热交换器的引导空气的护罩，分隔室外部的内部的护罩，包括围绕室外部的相对侧部和后侧的壳体的外部构件，以及机壳上的盖，以形成室外部分的上部外部，以及固定到屏障，护罩和外部构件的支架，用于防止屏障，护罩和外部构件之间的相对位置变化，由此紧固部件刚性，以增强紧固强度。

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