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1. 发明授权

US07060564B1 Memory device and method of simultaneous fabrication of core and periphery of same 有权
标题翻译：同时制造芯片和周边的记忆装置和方法
公开(公告)号：US07060564B1
公开(公告)日：2006-06-13
申请号：US10635089
申请日：2003-08-06
申请人： Inkuk Kang , Hiroyuki Kinoshita , Weidong Qian , Kelwin King Wai Ko , Yu Sun
发明人： Inkuk Kang , Hiroyuki Kinoshita , Weidong Qian , Kelwin King Wai Ko , Yu Sun
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.
摘要翻译：一种制造具有双位存储器单元的核心区域和逻辑电路的外围区域的存储器件的方法包括在半导体衬底的芯部和外围区域上形成电介质堆叠并从外围区域去除电介质堆叠。在外围区域上形成栅极电介质，随后在芯部和外围区域上形成第一导电层。在栅极电介质的形成和热处理之后，用作源极和漏极区的位线被植入核心区域。栅介质层之后的位线形成减少了横向位线扩散并减少了短沟道效应。

2. 发明授权

US06963108B1 Recessed channel 有权
标题翻译：嵌入渠道
公开(公告)号：US06963108B1
公开(公告)日：2005-11-08
申请号：US10683631
申请日：2003-10-10
申请人： Inkuk Kang , Hiroyuki Kinoshita , Jeff P. Erhardt , Emmanuil H. Lingunis
发明人： Inkuk Kang , Hiroyuki Kinoshita , Jeff P. Erhardt , Emmanuil H. Lingunis
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/04 , H01L29/78 , H01L29/792
CPC分类号： H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/045 , H01L29/66621 , H01L29/66833 , H01L29/7835 , H01L29/792
摘要： A memory cell with reduced short channel effects is described. A trench region is formed in a semiconductor substrate. A source region and a drain region are formed on opposing sides of the trench region, wherein a bottom of the source region and a bottom of the drain region are above a floor of the trench region. A gate dielectric layer is formed in the trench region of the semiconductor substrate between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A control gate is formed on the semiconductor substrate above the recessed channel region, wherein the control gate is separated from the recessed channel region by the gate dielectric layer.
摘要翻译：描述了具有减小的短通道效应的存储单元。在半导体衬底中形成沟槽区。源极区域和漏极区域形成在沟槽区域的相对侧上，其中源极区域的底部和漏极区域的底部在沟槽区域的地板的上方。在源极区域和漏极区域之间的半导体衬底的沟槽区域中形成栅极电介质层。在沟槽区域，源极区域和漏极区域之下形成凹陷沟道区域。控制栅极形成在凹陷沟道区域上方的半导体衬底上，其中控制栅极通过栅极介电层与凹陷沟道区分离。

3. 发明授权

US07288487B1 Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure 有权
标题翻译：抛光后的金属/氧化物蚀刻，以防止半导体结构的相邻特征之间的桥接
公开(公告)号：US07288487B1
公开(公告)日：2007-10-30
申请号：US11000870
申请日：2004-12-01
申请人： Inkuk Kang , Hiroyuki Kinoshita , Calvin T. Gabriel
发明人： Inkuk Kang , Hiroyuki Kinoshita , Calvin T. Gabriel
IPC分类号： H01L21/302
CPC分类号： H01L21/02074 , H01L21/76819 , H01L21/7684
摘要： Methods for eliminating and/or mitigating bridging and/or leakage caused by the contamination of a dielectric layer with fragments and/or residues of a conductive material are disclosed. The methods involve exposing a semiconductor substrate with a dielectric layer contaminated with fragments and/or residues of conductive materials to one or more conductor and/or dielectric etches. The disclosure by eliminating and/or mitigating metal bridging and/or leakage can provide one or more of the following advantages: high device reliability, decreased manufacturing cost, more efficient metallization, and increased performance.
摘要翻译：公开了用于消除和/或减轻由导电材料的碎片和/或残余物污染介电层引起的桥接和/或泄漏的方法。所述方法包括将被污染有导电材料的碎片和/或残余物的介电层暴露于一个或多个导体和/或介电蚀刻物。通过消除和/或减轻金属桥接和/或泄漏的公开可以提供一个或多个以下优点：高的器件可靠性，降低的制造成本，更有效的金属化和增加的性能。

4. 发明申请

US20060006552A1 Bond pad structure for copper metallization having increased reliability and method for fabricating same 有权
标题翻译：用于铜金属化的焊盘结构具有增加的可靠性及其制造方法
公开(公告)号：US20060006552A1
公开(公告)日：2006-01-12
申请号：US10887585
申请日：2004-07-08
申请人： Inkuk Kang , Hiroyuki Kinoshita , Boon-Yong Ang , Hajime Wada , Simon Chan , Cinti Chen
发明人： Inkuk Kang , Hiroyuki Kinoshita , Boon-Yong Ang , Hajime Wada , Simon Chan , Cinti Chen
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05073 , H01L2224/05147 , H01L2224/05181 , H01L2224/05554 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042
摘要： According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.
摘要翻译：根据一个示例性实施例，半导体管芯中的结构包括位于互连金属层中的金属焊盘，其中金属焊盘包括铜。该结构还包括位于金属焊盘上的层间电介质层。该结构还包括限定在层间电介质层中的端子通孔，其中端子通孔位于金属焊盘上。端子通孔仅沿着金属焊盘的一侧延伸。该结构还包括位于层间电介质层和端子通孔中的端子金属层。所述结构还包括位于所述端子金属层上的电介质衬垫，其中所述电介质衬垫中限定了焊盘开口，并且所述接合焊盘开口露出所述端子金属层的一部分。层间绝缘层位于端子金属层的暴露部分和金属焊盘之间。

5. 发明授权

US07242102B2 Bond pad structure for copper metallization having increased reliability and method for fabricating same 有权
标题翻译：用于铜金属化的焊盘结构具有增加的可靠性及其制造方法
公开(公告)号：US07242102B2
公开(公告)日：2007-07-10
申请号：US10887585
申请日：2004-07-08
申请人： Inkuk Kang , Hiroyuki Kinoshita , Boon-Yong Ang , Hajime Wada , Simon S Chan , Cinti X Chen
发明人： Inkuk Kang , Hiroyuki Kinoshita , Boon-Yong Ang , Hajime Wada , Simon S Chan , Cinti X Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/28
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05073 , H01L2224/05147 , H01L2224/05181 , H01L2224/05554 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042
摘要： According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.
摘要翻译：根据一个示例性实施例，半导体管芯中的结构包括位于互连金属层中的金属焊盘，其中金属焊盘包括铜。该结构还包括位于金属焊盘上的层间电介质层。该结构还包括限定在层间电介质层中的端子通孔，其中端子通孔位于金属焊盘上。端子通孔仅沿着金属焊盘的一侧延伸。该结构还包括位于层间电介质层和端子通孔中的端子金属层。所述结构还包括位于所述端子金属层上的电介质衬垫，其中所述电介质衬垫中限定了焊盘开口，并且所述接合焊盘开口露出所述端子金属层的一部分。层间绝缘层位于端子金属层的暴露部分和金属焊盘之间。

6. 发明授权

US08637918B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08637918B2
公开(公告)日：2014-01-28
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

7. 发明授权

US08487373B2 SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same 有权
标题翻译：具有不均匀隧道氧化物的SONOS存储单元及其制造方法
公开(公告)号：US08487373B2
公开(公告)日：2013-07-16
申请号：US12432441
申请日：2009-04-29
申请人： Shenqing Fang , Gang Xue , Wenmei Li , Inkuk Kang
发明人： Shenqing Fang , Gang Xue , Wenmei Li , Inkuk Kang
IPC分类号： H01L21/331
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/42352
摘要： Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
摘要翻译：公开了形成存储单元的方法。一种方法包括在半导体衬底中形成源极 - 漏极结构，其中源极 - 漏极结构包括圆顶顶表面和侧壁表面。在源极 - 漏极结构的顶壁和侧壁表面上形成氧化物层。形成在源极 - 漏极结构的顶表面上的氧化物层的部分的厚度大于在源极 - 漏极结构的侧壁表面上形成的氧化物层的部分的厚度。

8. 发明授权

US08076199B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08076199B2
公开(公告)日：2011-12-13
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

9. 发明授权

US07122465B1 Method for achieving increased control over interconnect line thickness across a wafer and between wafers 有权
标题翻译：用于实现跨晶片和晶片之间的互连线厚度的增加的控制的方法
公开(公告)号：US07122465B1
公开(公告)日：2006-10-17
申请号：US11003208
申请日：2004-12-02
申请人： Boon-Yong Ang , Cinti Xiaohua Chen , Simon S. Chan , Inkuk Kang
发明人： Boon-Yong Ang , Cinti Xiaohua Chen , Simon S. Chan , Inkuk Kang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/3212 , H01L21/7684
摘要： According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.
摘要翻译：根据一个示例性实施例，一种方法包括蚀刻ILD层中的沟槽的步骤，所述沟槽具有侧壁和底表面。该方法还包括确定沟槽的侧壁的高度。该方法还包括用互连金属填充沟槽，使得互连金属在沟槽之上延伸。根据该示例性实施例，该方法还包括执行CMP处理以去除互连金属的一部分。在本发明中，利用沟槽侧壁的高度来控制在CMP工艺中执行的抛光量。沟槽中的互连金属的剩余部分形成互连线，其中通过利用沟槽的侧壁的高度来控制互连线的厚度以控制CMP工艺中的抛光量。

10. 发明申请

US20100207191A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20100207191A1
公开(公告)日：2010-08-19
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/788 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

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