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1. 发明申请

US20100207191A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20100207191A1
公开(公告)日：2010-08-19
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing FANG , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/788 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

2. 发明申请

US20100276746A1 SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME 有权
标题翻译：具有非均质氧化锆的SONOS记忆体及其制造方法
公开(公告)号：US20100276746A1
公开(公告)日：2010-11-04
申请号：US12432441
申请日：2009-04-29
申请人： Shenqing FANG , Gang XUE , Wenmei LI , Inkuk KANG
发明人： Shenqing FANG , Gang XUE , Wenmei LI , Inkuk KANG
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/42352
摘要： Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
摘要翻译：公开了形成存储单元的方法。一种方法包括在半导体衬底中形成源极 - 漏极结构，其中源极 - 漏极结构包括圆顶顶表面和侧壁表面。在源极 - 漏极结构的顶壁和侧壁表面上形成氧化物层。形成在源极 - 漏极结构的顶表面上的氧化物层的部分的厚度大于在源极 - 漏极结构的侧壁表面上形成的氧化物层的部分的厚度。

3. 发明申请

US20090269916A1 METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SEMICIRCULAR TOP SURFACES AND ROUNDED TOP CORNERS AND EDGES 有权
标题翻译：具有半圆顶表面和圆顶顶角和边缘的晶体结构的记忆细胞的制备方法
公开(公告)号：US20090269916A1
公开(公告)日：2009-10-29
申请号：US12110974
申请日：2008-04-28
申请人： Inkuk KANG , Gang XUE , Shenqing FANG , Rinji SUGINO , Yi MA
发明人： Inkuk KANG , Gang XUE , Shenqing FANG , Rinji SUGINO , Yi MA
IPC分类号： H01L21/28 , H01L21/306
CPC分类号： H01L27/11568 , H01L29/66795 , H01L29/7854
摘要： Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.
摘要翻译：公开了制造具有半圆顶表面和圆顶顶表面拐角和边缘的FIN结构的方法。作为所公开的方法的一部分，在半导体衬底中形成FIN结构。 FIN结构包括具有拐角和边缘的顶表面。 FIN结构退火，其中退火导致顶表面具有半圆形形状，并且顶表面拐角和边缘被倒圆。

4. 发明申请

US20100133646A1 SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY 有权
标题翻译：自动对齐充电电池捕捉层隔离电荷捕捉闪存
公开(公告)号：US20100133646A1
公开(公告)日：2010-06-03
申请号：US12699635
申请日：2010-02-03
申请人： Shenqing FANG , Angela HUI , Shao-Yu TING , Inkuk KANG , Gang XUE
发明人： Shenqing FANG , Angela HUI , Shao-Yu TING , Inkuk KANG , Gang XUE
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/76224 , H01L27/11568
摘要： A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.
摘要翻译：公开了一种在圆形有源区域角上制造具有U形陷阱层的存储器件的方法。在本发明中，在形成电荷俘获层之前进行STI工艺。在STI处理之后，活动区域的尖角暴露，使其可用于四舍五入。四舍五入改善了存储设备的性能特征。在舍入处理之后，形成底部氧化物层，氮化物层和牺牲顶部氧化物层。施加到电荷捕获层的有机底部抗反射涂层被平坦化。现在蚀刻有机底部抗反射涂层，牺牲顶部氧化物层和氮化物层，而不在有源区域上蚀刻牺牲顶部氧化物层和氮化物层。在蚀刻之后，电荷捕获层具有横截面的U形外观。 U形陷阱层边缘允许增加堆积密度和集成度，同时保持捕集层之间的隔离。

5. 发明申请

US20110233647A1 METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER 有权
标题翻译：用于形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US20110233647A1
公开(公告)日：2011-09-29
申请号：US12891310
申请日：2010-09-27
申请人： Shenqing FANG , Angela HUI , Gang XUE , Alexander NICKEL , Kashmir SAHOTA , Scott BELL , Chun CHEN , Wai LO
发明人： Shenqing FANG , Angela HUI , Gang XUE , Alexander NICKEL , Kashmir SAHOTA , Scott BELL , Chun CHEN , Wai LO
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

6. 发明申请

US20120181601A1 METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER 有权
标题翻译：用于形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US20120181601A1
公开(公告)日：2012-07-19
申请号：US13428848
申请日：2012-03-23
申请人： Shenqing FANG , Angela HUI , Gang XUE , Alexander NICKEL , Kashmir SAHOTA , Scott BELL , Chun CHEN , Wai LO
发明人： Shenqing FANG , Angela HUI , Gang XUE , Alexander NICKEL , Kashmir SAHOTA , Scott BELL , Chun CHEN , Wai LO
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

7. 发明申请

US20110057315A1 MEMORY DEVICE PERIPHERAL INTERCONNECTS 有权
标题翻译：内存设备外设互连
公开(公告)号：US20110057315A1
公开(公告)日：2011-03-10
申请号：US12943679
申请日：2010-11-10
申请人： Shenqing FANG , Wenmei LI
发明人： Shenqing FANG , Wenmei LI
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/76816 , H01L23/485 , H01L27/1052 , H01L27/11529 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.
摘要翻译：在一个实施例中，集成电路存储器件包括衬底和连续地设置在衬底上的第一和第二级间介电层。外围设备中的一个或多个触点延伸穿过第一层间电介质层到相应的部件。一个或多个通孔和多个虚拟通孔延伸穿过周边区域中的第二层间电介质层。一个或多个外围通孔中的每一个延伸到相应的外围触点。外围的虚拟通孔位于外围通孔附近。

8. 发明申请

US20090289369A1 MEMORY DEVICE PERIPHERAL INTERCONNECTS AND METHOD OF MANUFACTURING 有权
标题翻译：存储器件外围互连和制造方法
公开(公告)号：US20090289369A1
公开(公告)日：2009-11-26
申请号：US12512960
申请日：2009-07-30
申请人： Shenqing FANG , Wenmei LI
发明人： Shenqing FANG , Wenmei LI
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/522 , H01L21/76816 , H01L23/485 , H01L27/1052 , H01L27/11529 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.
摘要翻译：在一个实施例中，集成电路存储器件包括衬底和连续地设置在衬底上的第一和第二级间介电层。外围设备中的一个或多个触点延伸穿过第一层间电介质层到相应的部件。一个或多个通孔和多个虚拟通孔延伸穿过周边区域中的第二层间电介质层。一个或多个外围通孔中的每一个延伸到相应的外围触点。外围的虚拟通孔位于外围通孔附近。

9. 发明申请

US20120168847A1 MEMORY WITH EXTENDED CHARGE TRAPPING LAYER 有权
标题翻译：具有扩展电荷捕获层的存储器
公开(公告)号：US20120168847A1
公开(公告)日：2012-07-05
申请号：US12982006
申请日：2010-12-30
申请人： Shenqing FANG , Tung-Sheng CHEN , Chun CHEN
发明人： Shenqing FANG , Tung-Sheng CHEN , Chun CHEN
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/4234 , H01L29/792
摘要： A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.
摘要翻译：存储器阵列包括多个位线和多个字线，栅极区域和电荷俘获层。电荷捕获层比字线宽; 电荷捕获层延伸超过栅极区域的边缘以便于捕获和去除电荷。

10. 发明申请

US20110057248A1 VARIED SILICON RICHNESS SILICON NITRIDE FORMATION 有权
标题翻译：变化硅硅酸盐氮化物形成
公开(公告)号：US20110057248A1
公开(公告)日：2011-03-10
申请号：US12556199
申请日：2009-09-09
申请人： Yi MA , Shenqing FANG , Robert OGLE
发明人： Yi MA , Shenqing FANG , Robert OGLE
IPC分类号： H01L29/792 , H01L21/31
CPC分类号： H01L29/518 , H01L21/0217 , H01L21/022 , H01L21/0228 , H01L21/28282 , H01L21/3141 , H01L21/3185 , H01L29/4234 , H01L29/511 , H01L29/792
摘要： A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.
摘要翻译：在一个实施例中，一种方法可以包括在衬底上形成隧道氧化物层。此外，该方法可以包括通过原子层沉积在隧道氧化物层上沉积第一层氮化硅。注意，第一层氮化硅包括第一硅丰富度。该方法还可以包括通过原子层沉积在第一氮化硅层上沉积第二层氮化硅。第二层氮化硅包括与第一硅浓度不同的第二硅浓度。

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