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1. 发明授权

US07060564B1 Memory device and method of simultaneous fabrication of core and periphery of same 有权
标题翻译：同时制造芯片和周边的记忆装置和方法
公开(公告)号：US07060564B1
公开(公告)日：2006-06-13
申请号：US10635089
申请日：2003-08-06
申请人： Inkuk Kang , Hiroyuki Kinoshita , Weidong Qian , Kelwin King Wai Ko , Yu Sun
发明人： Inkuk Kang , Hiroyuki Kinoshita , Weidong Qian , Kelwin King Wai Ko , Yu Sun
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.
摘要翻译：一种制造具有双位存储器单元的核心区域和逻辑电路的外围区域的存储器件的方法包括在半导体衬底的芯部和外围区域上形成电介质堆叠并从外围区域去除电介质堆叠。在外围区域上形成栅极电介质，随后在芯部和外围区域上形成第一导电层。在栅极电介质的形成和热处理之后，用作源极和漏极区的位线被植入核心区域。栅介质层之后的位线形成减少了横向位线扩散并减少了短沟道效应。

2. 发明授权

US07432178B2 Bit line implant 有权
标题翻译：位线植入
公开(公告)号：US07432178B2
公开(公告)日：2008-10-07
申请号：US11254769
申请日：2005-10-21
申请人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
发明人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
IPC分类号： H01L21/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
摘要翻译：公开了一种用于执行位线植入的方法。该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。该组结构的每个结构包括多晶硅部分和硬掩模部分。该组结构的第一结构与该组结构的第二结构分开小于100纳米。该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

3. 发明申请

US20070093042A1 Bit line implant 有权
标题翻译：位线植入
公开(公告)号：US20070093042A1
公开(公告)日：2007-04-26
申请号：US11254769
申请日：2005-10-21
申请人： Angela Hui , Jean Yang , Yu Sun , Mark Ramsbey , Weidong Qian
发明人： Angela Hui , Jean Yang , Yu Sun , Mark Ramsbey , Weidong Qian
IPC分类号： H01L21/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
摘要翻译：公开了一种用于执行位线植入的方法。该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。该组结构的每个结构包括多晶硅部分和硬掩模部分。该组结构的第一结构与该组结构的第二结构分开小于100纳米。该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

4. 发明授权

US07307002B2 Non-critical complementary masking method for poly-1 definition in flash memory device fabrication 有权
标题翻译：闪存器件制造中poly-1定义的非关键互补掩模方法
公开(公告)号：US07307002B2
公开(公告)日：2007-12-11
申请号：US11099339
申请日：2005-04-04
申请人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher H. Raeder , Christopher M. Foster , Harpreet Kaur Sachar , Kashmir Singh Sahota
发明人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher H. Raeder , Christopher M. Foster , Harpreet Kaur Sachar , Kashmir Singh Sahota
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , H01L21/3212 , H01L21/32139 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543 , H01L27/11568
摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
摘要翻译：公开了一种用于在半导体晶片中定义多晶硅层的方法。使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

5. 发明授权

US07202540B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07202540B2
公开(公告)日：2007-04-10
申请号：US11066567
申请日：2005-02-28
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并掺杂杂质的重掺杂深杂质区域（7b）其浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区域（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

6. 发明授权

US06306713B1 Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer 有权
标题翻译：用于使用次级间隔件形成用于盐水门的自对准接触件和局部互连的方法
公开(公告)号：US06306713B1
公开(公告)日：2001-10-23
申请号：US09799469
申请日：2001-03-05
申请人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Hiroyuki Kinoshita
发明人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76895 , H01L2924/3011
摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers. The multi-layer structures and the source and drain regions are silicided and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A photoresist contact mask is deposited, processed, and used to form core contact openings over the core region, which expose the multi-layer structure in addition to the source and drain regions while covering the peripheral region. Protective secondary sidewall spacers are formed in the core contact openings over the exposed multi-layer structures. A second photoresist contact mask is deposited, processed, and used to form peripheral local interconnect openings over the peripheral region which the source and drain regions and portions of the plurality of multi-layer structures in the peripheral region while covering the core region. A conductive material is deposited over the dielectric layer and in the core contact and peripheral local interconnect openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。围绕多层结构形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入。多层结构和源极和漏极区域被硅化，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。光致抗蚀剂接触掩模被沉积，加工并用于在芯部区域上形成芯接触开口，除了覆盖周边区域之外，还暴露多层结构以及源极和漏极区域。保护性次级侧壁间隔件形成在暴露的多层结构上的芯接触开口中。第二光致抗蚀剂接触掩模被沉积，加工并用于在外围区域上形成周边局部互连开口，周边区域是外围区域的源极和漏极区域以及多个多层结构的部分，同时覆盖芯部区域。导电材料沉积在电介质层上，并在芯接触和外围局部互连开口中沉积，并进行化学机械平面化以去除电介质层上的导电材料，使得导电材料在芯和外围接触开口中被隔离。

7. 发明授权

US07759745B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07759745B2
公开(公告)日：2010-07-20
申请号：US11656437
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b）浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

8. 发明授权

US07683440B2 Semiconductor memory device 有权
公开(公告)号：US07683440B2
公开(公告)日：2010-03-23
申请号：US11656437
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

9. 发明授权

US07482226B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07482226B2
公开(公告)日：2009-01-27
申请号：US11656438
申请日：2007-01-23
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b）浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

10. 发明申请

US20070205454A1 Dual storage node memory 有权
标题翻译：双存储节点存储器
公开(公告)号：US20070205454A1
公开(公告)日：2007-09-06
申请号：US11702845
申请日：2007-02-05
申请人： Fred Cheung , Hiroyuki Kinoshita , Chungho Lee , Yu Sun , Chi Chang
发明人： Fred Cheung , Hiroyuki Kinoshita , Chungho Lee , Yu Sun , Chi Chang
IPC分类号： G11C16/04
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521
摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.
摘要翻译：本发明的实施例涉及存储单元。存储单元包括第一电荷存储元件和第二电荷存储元件，其中第一和第二电荷存储元件包括氮化物。存储单元还包括形成在第一和第二电荷存储元件之间的绝缘层。绝缘层提供第一和第二电荷存储元件之间的绝缘。

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