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1. 发明授权

US6029241A Processor architecture scheme having multiple bank address override sources for supplying address values and method therefor 失效
标题翻译：具有用于提供地址值的多个存储体地址覆盖源的处理器架构方案及其方法
公开(公告)号：US6029241A
公开(公告)日：2000-02-22
申请号：US959405
申请日：1997-10-28
申请人： Igor Wojewoda , Sumit Mitra , Rodney J. Drake
发明人： Igor Wojewoda , Sumit Mitra , Rodney J. Drake
IPC分类号： G06F9/34 , G06F9/30 , G06F9/35 , G06F12/06
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30138 , G06F9/35
摘要： A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor architecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode. An instruction register is coupled to the selection circuit for supplying a bank address values for an instruction to be executed in a direct long addressing mode and for supplying a register address within a bank for the instruction to be executed in a direct short addressing mode.
摘要翻译：一种处理器架构方案，其允许对多个寻址模式进行编码，并且具有用于生成存储体地址值的多个源。处理器架构方案具有用于执行指令集的中央处理单元（CPU）。数据存储器耦合到CPU。数据存储器用于存储和传输数据到和从CPU传输数据。数据存储器被分成多个存储体，其中多个存储体中的一个存储体是用于通用和专用寄存器的专用库。选择电路耦合到数据存储器。选择电路用于选择多个源之一以产生存储体地址值。存储体选择寄存器耦合到选择电路。存储体选择寄存器用于提供要在直接短寻址模式下执行的指令的存储体地址值。指令寄存器耦合到选择电路，用于提供用于以直接长寻址模式执行的指令的存储体地址值，以及用于以直接短寻址模式提供要执行的指令的存储体内的寄存器地址。

2. 发明授权

US06321319B2 Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction 有权
公开(公告)号：US06321319B2
公开(公告)日：2001-11-20
申请号：US09756304
申请日：2001-01-08
申请人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
发明人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
IPC分类号： G06F1202
CPC分类号： G06F9/3802 , G06F9/3816
摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

3. 发明授权

US6057705A Programmable pin designation for semiconductor devices 失效
标题翻译：半导体器件的可编程引脚名称
公开(公告)号：US6057705A
公开(公告)日：2000-05-02
申请号：US85826
申请日：1998-05-28
申请人： Igor Wojewoda , Rodney J. Drake , Brian E. Boles
发明人： Igor Wojewoda , Rodney J. Drake , Brian E. Boles
IPC分类号： G06F3/00 , G06F1/22 , G06F15/78 , H03K19/173 , G06F7/38
CPC分类号： G06F1/22 , H03K19/173 , H03K19/1731
摘要： The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programming logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer's requirements. The invention is to exist on a single, monolithic semiconductor device.
摘要翻译：本发明允许编程器将半导体器件上的一个或多个引脚指定为除了预定的一组地址线之外的地址引脚或作为替代的I / O引脚。本发明的目的是为程序员提供精确定义特定应用所需的地址总线的特定大小的能力。本发明由编程端口，可选的编程逻辑，配置逻辑，选择逻辑和可以根据编程器的要求进行配置的一组引脚组成。本发明存在于单个单片半导体器件上。

4. 发明授权

US6098160A Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor 失效
标题翻译：用于在单个周期内输出间接寻址模式地址的数据指针及其方法
公开(公告)号：US6098160A
公开(公告)日：2000-08-01
申请号：US959559
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
发明人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
IPC分类号： G06F9/35 , G06F12/00
CPC分类号： G06F9/35
摘要： A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
摘要翻译：一种数据指针，用于在多个间接寻址模式中选定的一个周期内在单个周期内生成间接寻址模式地址。数据指针与处理器架构方案一起使用，该方案允许对多种寻址模式进行编码。数据指针寄存器耦合到处理器架构方案，用于存储要在简单的间接寻址模式中使用的操作数的当前地址。增量器被耦合到数据指针寄存器，用于以简单的间接数据寻址模式递增一个操作数的当前地址一个设定的数字，从而产生要以具有自动预压缩的间接寻址方式使用的操作数的地址。加法器耦合到数据指针寄存器，用于将要在简单间接数据寻址模式中使用的操作数的当前地址与偏移号组合，从而生成要在具有偏移量的间接寻址模式中使用的操作数的地址。多路复用器电路耦合到数据指针寄存器的输出，加法器的输出端和加法器的输出端，用于选择期望的间接寻址模式地址。

5. 发明授权

US06243798B1 Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction 失效
标题翻译：用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的计算机系统
公开(公告)号：US06243798B1
公开(公告)日：2001-06-05
申请号：US08958940
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
发明人： Rodney J. Drake , Randy L. Yach , Joseph W. Triece , Jennifer Chiao , Igor Wojewoda , Steve Allen
IPC分类号： G06F1202
CPC分类号： G06F9/3802 , G06F9/3816
摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.
摘要翻译：用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的系统，从而允许处理器系统增加存储器空间而不降低性能。第一地址总线耦合到线性化程序存储器，用于发送要获取的指令的地址到线性化程序存储器。指针耦合到第一地址总线，用于存储要获取的线性化程序存储器中的当前指令的地址位置，并将要提取的当前指令的地址位置放置在第一地址总线上。提供第二地址总线，其一端耦合到程序存储器的输出端，第二端耦合到第一地址总线。第二地址总线用于在双字跳转指令的第一字的操作数的地址已经被放置在第一地址总线上之后，将两字跳转指令的第二字的操作数的地址放置在第一地址总线上地址总线这允许将第一个字和第二个字的地址组合起来，以与单个字跳转指令相同的周期数来提供两个字跳转指令的完整地址值。

6. 发明授权

US5905880A Robust multiple word instruction and method therefor 失效
标题翻译：强大的多字指令及其方法
公开(公告)号：US5905880A
公开(公告)日：1999-05-18
申请号：US937682
申请日：1997-09-29
申请人： Rodney J. Drake , Joseph W. Triece
发明人： Rodney J. Drake , Joseph W. Triece
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30069 , G06F9/30149
摘要： An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.
摘要翻译：具有鲁棒多字指令的微控制器指令集。指令集具有多个指令，其中多个指令包括单字指令和多个字指令。至少一个位位于所有多个字指令的所有非首字中的预定位置。如果在多字指令中执行任何后续字之前未执行多字指令的第一个字，该位将被微控制器解码为无操作位。

7. 发明授权

US5859553A System and method for a glitchless transition between differing delay paths 失效
标题翻译：不同延迟路径之间的无故障转换的系统和方法
公开(公告)号：US5859553A
公开(公告)日：1999-01-12
申请号：US779804
申请日：1997-01-08
申请人： Rodney J. Drake
发明人： Rodney J. Drake
IPC分类号： H03K5/1252 , H03K5/13 , H03K17/00 , H03K17/16 , H03K5/159
CPC分类号： H03K17/005 , H03K17/16 , H03K5/1252 , H03K5/13
摘要： A system for switching between a signal having delay paths of differing magnitudes without generating any glitches and false edges uses a no delay circuit for outputting a signal having no delay and a delay output circuit for outputting a delayed form of the signal. The signals are inputted to a multiplexer. The multiplexer will output at least one of the signals. Control circuitry is coupled to the multiplexer for signalling the multiplexer to output at least one of the signals. The control circuitry will control the switching of the multiplexer so that when the output of the multiplexer switches from a signal having no delay to a delayed form of the signal, or when the output of the multiplexer switches from a delayed form of the signal to a signal having no delay, no glitches or false edges are generated.
摘要翻译：用于在具有不同幅度的延迟路径的信号之间进行切换而不产生任何毛刺和假边缘的系统使用用于输出无延迟的信号的无延迟电路和用于输出延迟形式的信号的延迟输出电路。信号被输入到多路复用器。复用器将输出至少一个信号。控制电路耦合到多路复用器，用于发信号通知多路复用器以输出至少一个信号。控制电路将控制多路转换器的切换，使得当多路复用器的输出从没有延迟的信号切换到信号的延迟形式时，或者当多路复用器的输出从信号的延迟形式切换到信号没有延迟，不产生毛刺或伪边缘。

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