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1. 发明申请

US20070247961A1 MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT 有权
标题翻译：存储器控制器，具有需要的信号输出
公开(公告)号：US20070247961A1
公开(公告)日：2007-10-25
申请号：US11768107
申请日：2007-06-25
申请人： Ian Shaeffer , Bret Stott , Benedict Lau
发明人： Ian Shaeffer , Bret Stott , Benedict Lau
IPC分类号： G11C8/00
CPC分类号： G11C7/1063 , G06F12/00 , G06F13/1689 , G11C7/1072
摘要： A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
摘要翻译：具有时间交错请求信号输出的存储器控制器。根据第一编程值产生相对于第一时钟信号的相位偏移的第一定时信号，并且根据第二编程值产生相对于第一时钟信号的相位偏移的第二定时信号。响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

2. 发明申请

US20090206867A1 Self-Test Method for Interface Circuit 有权
标题翻译：接口电路自检方法
公开(公告)号：US20090206867A1
公开(公告)日：2009-08-20
申请号：US12430832
申请日：2009-04-27
申请人： Bret Stott , Philip Yeung , John W. Brooks , Benedict Lau , Chanh V. Tran , Eugene C. Ho
发明人： Bret Stott , Philip Yeung , John W. Brooks , Benedict Lau , Chanh V. Tran , Eugene C. Ho
IPC分类号： G01R31/26
CPC分类号： G01R31/31716 , G11C29/022
摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.
摘要翻译：描述了集成电路。集成电路包括包括发射机和接收机的接口电路。集成电路中的发生器选择性地耦合到发射机。发电机将提供在测试操作模式期间由发射机输出的测试序列。集成电路中的存储器选择性地耦合到发生器和接收器。存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。集成电路中的逻辑电路是比较测试序列和信号。

3. 发明授权

US07535242B2 Interface test circuit 失效
标题翻译：接口测试电路
公开(公告)号：US07535242B2
公开(公告)日：2009-05-19
申请号：US11417964
申请日：2006-05-03
申请人： Bret Stott , Philip Yeung , John W. Brooks , Benedict Lau , Chanh V. Tran , Eugene C. Ho
发明人： Bret Stott , Philip Yeung , John W. Brooks , Benedict Lau , Chanh V. Tran , Eugene C. Ho
IPC分类号： G01R31/26
CPC分类号： G01R31/31716 , G11C29/022
摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.
摘要翻译：描述了集成电路。集成电路包括包括发射机和接收机的接口电路。集成电路中的发生器选择性地耦合到发射机。发生器将提供在测试操作模式期间由发射器输出的测试序列。集成电路中的存储器选择性地耦合到发生器和接收器。存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。集成电路中的逻辑电路是比较测试序列和信号。

4. 发明申请

US20070257693A1 Interface test circuit 失效
标题翻译：接口测试电路
公开(公告)号：US20070257693A1
公开(公告)日：2007-11-08
申请号：US11417964
申请日：2006-05-03
申请人： Bret Stott , Philip Yeung , John Brooks , Benedict Lau , Chanh Tran , Eugene Ho
发明人： Bret Stott , Philip Yeung , John Brooks , Benedict Lau , Chanh Tran , Eugene Ho
IPC分类号： G01R31/02
CPC分类号： G01R31/31716 , G11C29/022
摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.
摘要翻译：描述了集成电路。集成电路包括包括发射机和接收机的接口电路。集成电路中的发生器选择性地耦合到发射机。发生器将提供在测试操作模式期间由发射器输出的测试序列。集成电路中的存储器选择性地耦合到发生器和接收器。存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。集成电路中的逻辑电路是比较测试序列和信号。

5. 发明申请

US20070086268A1 Memory controller with staggered request signal output 有权
标题翻译：具有交错请求信号输出的存储控制器
公开(公告)号：US20070086268A1
公开(公告)日：2007-04-19
申请号：US11252957
申请日：2005-10-17
申请人： Ian Shaetfer , Bret Stott , Benedict Lau
发明人： Ian Shaetfer , Bret Stott , Benedict Lau
IPC分类号： G11C8/00
CPC分类号： G11C7/1063 , G06F12/00 , G06F13/1689 , G11C7/1072
摘要： A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
摘要翻译：具有时间交错请求信号输出的存储器控制器。根据第一编程值产生相对于第一时钟信号的相位偏移的第一定时信号，并且根据第二编程值产生相对于第一时钟信号的相位偏移的第二定时信号。响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

6. 发明授权

US08378699B2 Self-test method for interface circuit 有权
标题翻译：接口电路的自检方法
公开(公告)号：US08378699B2
公开(公告)日：2013-02-19
申请号：US12430832
申请日：2009-04-27
申请人： Bret Stott , Philip Yeung , John W. Brooks , Benedict Lau , Chanh V. Tran , Eugene C. Ho
发明人： Bret Stott , Philip Yeung , John W. Brooks , Benedict Lau , Chanh V. Tran , Eugene C. Ho
IPC分类号： G01R31/20 , G01R31/26
CPC分类号： G01R31/31716 , G11C29/022
摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.
摘要翻译：描述了集成电路。集成电路包括包括发射机和接收机的接口电路。集成电路中的发生器选择性地耦合到发射机。发生器将提供在测试操作模式期间由发射器输出的测试序列。集成电路中的存储器选择性地耦合到发生器和接收器。存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。集成电路中的逻辑电路是比较测试序列和信号。

7. 发明授权

US08151133B2 Method for calibrating read operations in a memory system 有权
标题翻译：用于校准存储器系统中的读取操作的方法
公开(公告)号：US08151133B2
公开(公告)日：2012-04-03
申请号：US12477092
申请日：2009-06-02
申请人： Jade M. Kizer , Sivakumar Doraiswamy , Benedict Lau
发明人： Jade M. Kizer , Sivakumar Doraiswamy , Benedict Lau
IPC分类号： G06F1/12
CPC分类号： G11C11/4076 , G06F13/1689 , G06F13/405 , G11C7/222 , G11C8/18 , G11C11/4063 , G11C11/4072 , G11C11/4096
摘要： A method of calibrating read operations in a memory system is disclosed. The method involves placing a memory controller in a calibration mode, and performing a series of dummy read operations. Each of the read operations performs a read of pre-specified data stored in at least one memory component while using different ones of delayed enable signals. Data read from respective dummy read operations is compared to identify successful read operations while the timing information from successful read operations is compared to identify a suitable delayed enable signal.
摘要翻译：公开了一种在存储器系统中校准读取操作的方法。该方法涉及将存储器控制器置于校准模式，并执行一系列虚拟读取操作。每个读取操作在使用不同的延迟使能信号的同时执行存储在至少一个存储器组件中的预先指定数据的读取。将从相应的虚拟读取操作读取的数据进行比较以识别成功读取操作，同时比较来自成功读取操作的定时信息以识别合适的延迟使能信号。

8. 发明申请

US20090240968A1 METHOD FOR CALIBRATING READ OPERATIONS IN A MEMORY SYSTEM 有权
标题翻译：用于校准读取存储器系统中的操作的方法
公开(公告)号：US20090240968A1
公开(公告)日：2009-09-24
申请号：US12477092
申请日：2009-06-02
申请人： Jade M. Kizer , Sivakumar Doraiswamy , Benedict Lau
发明人： Jade M. Kizer , Sivakumar Doraiswamy , Benedict Lau
IPC分类号： G06F1/12
CPC分类号： G11C11/4076 , G06F13/1689 , G06F13/405 , G11C7/222 , G11C8/18 , G11C11/4063 , G11C11/4072 , G11C11/4096
摘要： A method of calibrating read operations in a memory system is disclosed. The method involves placing a memory controller in a calibration mode, and performing a series of dummy read operations. Each of the read operations performs a read of pre-specified data stored in at least one memory component while using different ones of delayed enable signals. Data read from respective dummy read operations is compared to identify successful read operations while the timing information from successful read operations is compared to identify a suitable delayed enable signal.
摘要翻译：公开了一种在存储器系统中校准读取操作的方法。该方法涉及将存储器控制器置于校准模式，并执行一系列虚拟读取操作。每个读取操作在使用不同的延迟使能信号的同时执行存储在至少一个存储器组件中的预先指定数据的读取。将从相应的虚拟读取操作读取的数据进行比较以识别成功读取操作，同时比较来自成功读取操作的定时信息以识别合适的延迟使能信号。

9. 发明授权

US07525338B2 Calibration methods and circuits for optimized on-die termination 有权
标题翻译：用于优化片上端接的校准方法和电路
公开(公告)号：US07525338B2
公开(公告)日：2009-04-28
申请号：US11639119
申请日：2006-12-13
申请人： Huy M. Nguyen , Vijay Gadde , Benedict Lau
发明人： Huy M. Nguyen , Vijay Gadde , Benedict Lau
IPC分类号： H03K19/003
CPC分类号： H03K19/0005 , H03K5/24 , H03K19/01 , H03K21/08 , H04L25/0278 , H04L25/0298
摘要： Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.
摘要翻译：描述了便于通过一个或多个信号传输线路互连的驱动器管芯和接收器管芯之间的高速通信的管芯端接（ODT）系统和方法。根据一个实施例的ODT控制系统校准并维持终端电阻和驱动电流以产生最佳输出摆幅电压。用于校准参考电阻的比较电路也用于校准驱动电流。一些实施例中的终端元件被分成两个可调节的电阻部分，它们都被设计成最小化容性负载。一部分被优化以产生相对较高的调节范围，而另一部分被优化用于微调和无故障切换。

10. 发明申请

US20060188051A1 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US20060188051A1
公开(公告)日：2006-08-24
申请号：US11406557
申请日：2006-04-18
申请人： Kevin Donnelly , Pak Chau , Mark Horowitz , Thomas Lee , Mark Johnson , Benedict Lau , Leung Yu , Bruno Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Tran , Donald Stark , Nhat Nguyen
发明人： Kevin Donnelly , Pak Chau , Mark Horowitz , Thomas Lee , Mark Johnson , Benedict Lau , Leung Yu , Bruno Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Tran , Donald Stark , Nhat Nguyen
IPC分类号： H04L7/00
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
摘要翻译：适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟从所述多个相位矢量中选择并具有第二参考时钟。

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