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1. 发明申请

US20060188051A1 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US20060188051A1
公开(公告)日：2006-08-24
申请号：US11406557
申请日：2006-04-18
申请人： Kevin Donnelly , Pak Chau , Mark Horowitz , Thomas Lee , Mark Johnson , Benedict Lau , Leung Yu , Bruno Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Tran , Donald Stark , Nhat Nguyen
发明人： Kevin Donnelly , Pak Chau , Mark Horowitz , Thomas Lee , Mark Johnson , Benedict Lau , Leung Yu , Bruno Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Tran , Donald Stark , Nhat Nguyen
IPC分类号： H04L7/00
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
摘要翻译：适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟从所述多个相位矢量中选择并具有第二参考时钟。

2. 发明申请

US20070118711A1 TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY 有权
公开(公告)号：US20070118711A1
公开(公告)日：2007-05-24
申请号：US11624966
申请日：2007-01-19
申请人： Kevin Donnelly , Mark Johnson , Chanh Tran , John Dillon , Nancy Dillon
发明人： Kevin Donnelly , Mark Johnson , Chanh Tran , John Dillon , Nancy Dillon
IPC分类号： G06F13/00
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

3. 发明申请

US20070011426A1 TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY 有权
标题翻译：具有延迟对准电路的收发器
公开(公告)号：US20070011426A1
公开(公告)日：2007-01-11
申请号：US11465230
申请日：2006-08-17
申请人： Kevin Donnelly , Mark Johnson , Chanh Tran , John Dillon , Nancy Dillon
发明人： Kevin Donnelly , Mark Johnson , Chanh Tran , John Dillon , Nancy Dillon
IPC分类号： G06F13/00
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
摘要翻译：在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

4. 发明申请

US20050160247A1 Transceiver with latency alignment circuitry 有权
标题翻译：具有延迟对准电路的收发器
公开(公告)号：US20050160247A1
公开(公告)日：2005-07-21
申请号：US11078577
申请日：2005-03-11
申请人： John Dillon , Nancy Dillon , Kevin Donnelly , Mark Johnson , Chanh Tran
发明人： John Dillon , Nancy Dillon , Kevin Donnelly , Mark Johnson , Chanh Tran
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.
摘要翻译：收发器设备包括发射器，用于将信号通过多个导体传输到存储器件。接口从耦合到控制器设备的串行通信路径接收控制信息。控制信息作为使用发射机的信号提供给存储装置。寄存器存储控制参数，该控制参数指定使用发射机将多个导体发送到存储器件的信号的驱动强度调整。

5. 发明授权

US06643752B1 Transceiver with latency alignment circuitry 有权
标题翻译：具有延迟对准电路的收发器
公开(公告)号：US06643752B1
公开(公告)日：2003-11-04
申请号：US09458582
申请日：1999-12-09
申请人： Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon
发明人： Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon
IPC分类号： G06F1200
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.
摘要翻译：描述收发器系统。次存储器模块耦合到主信道，用于从控制器接收数据和信号。辅助存储器模块包括用于将数据和控制信号发送到存储器的存储器和辅助通道。次存储器模块还包括耦合到主信道和次信道的收发器。收发器被设计为将次级通道与主通道电隔离。收发器是一个低延迟中继器，允许来自控制器的数据和控制信号到达存储器，使得来自控制器的数据请求的等待时间与收发器与控制器的距离无关。

6. 发明授权

US08458426B2 Transceiver with latency alignment circuitry 有权
标题翻译：具有延迟对准电路的收发器
公开(公告)号：US08458426B2
公开(公告)日：2013-06-04
申请号：US11624966
申请日：2007-01-19
申请人： Kevin Donnelly , Mark Johnson , Chanh Tran , Nancy D. Dillon
发明人： Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon
IPC分类号： G06F12/00
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
摘要翻译：在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

7. 发明申请

US20050149685A1 Transceiver with latency alignment circuitry 有权
标题翻译：具有延迟对准电路的收发器
公开(公告)号：US20050149685A1
公开(公告)日：2005-07-07
申请号：US11058333
申请日：2005-02-15
申请人： Kevin Donnelly , Mark Johnson , Chanh Tran , John Dillon , Nancy Dillon
发明人： Kevin Donnelly , Mark Johnson , Chanh Tran , John Dillon , Nancy Dillon
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.
摘要翻译：收发机包括第一接口，用于通过第一信道从存储器装置接收第一信号。发射机通过第二信道将表示第一信号的第二信号发送到主设备。多个寄存器存储由主设备提供的多个值。多个值包括第一值，该第一值指定由发送器向主设备发送的第二信号的发送定时调整。

8. 发明授权

US08086812B2 Transceiver with latency alignment circuitry 有权
标题翻译：具有延迟对准电路的收发器
公开(公告)号：US08086812B2
公开(公告)日：2011-12-27
申请号：US11465230
申请日：2006-08-17
申请人： Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon , Nancy D. Dillon, legal representative
发明人： Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon
IPC分类号： G06F12/00
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
摘要翻译：在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

9. 发明申请

US20050105371A1 Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement 有权
标题翻译：集成电路结合具有双重相对的解码器布置的三维存储器阵列
公开(公告)号：US20050105371A1
公开(公告)日：2005-05-19
申请号：US10774818
申请日：2004-02-09
申请人： Mark Johnson , Thomas Lee , James Cleeves
发明人： Mark Johnson , Thomas Lee , James Cleeves
IPC分类号： G11C11/56 , G11C17/14 , G11C17/16 , H01L27/102 , G11C8/00
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

10. 发明授权

US10328467B2 Automatic cleaning at a self-service dispensing device 有权
公开(公告)号：US10328467B2
公开(公告)日：2019-06-25
申请号：US13326545
申请日：2011-12-15
申请人： Mark Johnson , Gregg Fallon , Tommy Williams , Kenn Armstrong , Dave Gregerson
发明人： Mark Johnson , Gregg Fallon , Tommy Williams , Kenn Armstrong , Dave Gregerson
IPC分类号： A47L13/17 , B08B1/00 , B08B1/02 , G07F19/00 , G07F7/00 , G07F7/08
摘要： Methods are provided for automatic cleaning of gripper belts and rollers within a self-service dispensing device. In an embodiment, a cleaning station located in a storage bin of the dispensing device is used to perform the automatic cleaning. The cleaning station is retrofitted into an existing storage bin of the dispensing device. In another embodiment, an interactive slot mechanism of the dispensing device is modified to hold a cleaning case and provide cleaning fluid to clean the belts and/or rollers. In another embodiment, a cleaning case contains a reservoir of cleaning fluid and a pad saturated with the cleaning fluid to clean the internal belts and roller. Furthermore the cleaning case may contain an automatic lid to maintain saturation of the pads and to keep debris from the cleaning case itself.

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