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1. 发明申请

WO2014105167A1 APPARATUS AND METHOD FOR PAGE WALK EXTENSION FOR ENHANCED SECURITY CHECKS 审中-公开
标题翻译：用于增强安全检查的页面扩展的装置和方法
公开(公告)号：WO2014105167A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047423
申请日：2013-06-24
申请人： INTEL CORPORATION , HILDESHEIM, Gur , ANATI, Ittai , SHAIF, Hisham , RAIKIN, Shlomo , GERZON, Gideon , SAVAGAONKAR, Uday R. , ROZAS, Carlos V. , MCKEEN, Francis X. , GOLDSMITH, Michael A. , DEWAN, Prashant
发明人： HILDESHEIM, Gur , ANATI, Ittai , SHAIF, Hisham , RAIKIN, Shlomo , GERZON, Gideon , SAVAGAONKAR, Uday R. , ROZAS, Carlos V. , MCKEEN, Francis X. , GOLDSMITH, Michael A. , DEWAN, Prashant
IPC分类号： G06F21/78
CPC分类号： G06F12/145 , G06F12/084 , G06F12/1027 , G06F12/1483 , G06F21/53
摘要： An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.
摘要翻译：一种用于由处理器管理保护表的装置和方法。例如，根据本发明的一个实施例的处理器包括：保护表管理逻辑，用于管理保护表，所述保护表具有每个受保护页面的条目或存储器中的每组受保护页面; 其中保护表管理逻辑防止用户应用程序代码和操作系统程序代码直接访问保护表，但允许处理器直接访问。

2. 发明申请

WO2014004151A2 VIRTUAL MEMORY ADDRESS RANGE REGISTER 审中-公开
标题翻译：虚拟内存地址范围注册
公开(公告)号：WO2014004151A2
公开(公告)日：2014-01-03
申请号：PCT/US2013/046169
申请日：2013-06-17
申请人： INTEL CORPORATION , HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SAVAGAONKAR, Uday , MCKEEN, Francis , ROZAS, Carlos , GOLDSMITH, Michael , DEWAN, Prashant
发明人： HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SAVAGAONKAR, Uday , MCKEEN, Francis , ROZAS, Carlos , GOLDSMITH, Michael , DEWAN, Prashant
IPC分类号： G06F12/08
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

3. 发明申请

WO2013095467A1 A BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE 审中-公开
标题翻译：一个平衡的P-LRU树，一个“多个3”的方式高速缓存
公开(公告)号：WO2013095467A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066652
申请日：2011-12-21
申请人： INTEL CORPORATION , BASEL, Adi , HILDESHEIM, Gur , RAIKIN, Shlomo , CHAPPELL, Robert , KIM, Ho-Seop , BHATIA, Rohit
发明人： BASEL, Adi , HILDESHEIM, Gur , RAIKIN, Shlomo , CHAPPELL, Robert , KIM, Ho-Seop , BHATIA, Rohit
IPC分类号： G06F1/00
CPC分类号： G06F12/122 , G06F3/0604 , G06F12/00 , G06F12/0842 , G06F12/0864 , G06F12/124 , G06F12/125
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a "multiple of 3" number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N-1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a "multiple of 5" number of cache ways, and variations of the "multiple of 3" number of cache ways.
摘要翻译：根据本文公开的实施例，提供了用于实现用于“3”倍的方式高速缓存的平衡P-LRU树的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。在这样的实施例中，多个方式包括一个数量是三的倍数，而不是二的幂，并且其中多个方式被组织成多对。在这样的实施例中，装置还包括用于多个对中的每一对的单个位，其中每个单个位将用作表示相关联的方式的中间级决策节点和具有正好两个单独位的根级判定节点指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

4. 发明申请

WO2014105151A1 APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB) 审中-公开
标题翻译：多页翻页预处理缓存器（TLB）的设备和方法
公开(公告)号：WO2014105151A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046910
申请日：2013-06-20
申请人： INTEL CORPORATION , RAIKIN, Shlomo , HAMAMA, Oren , CHAPPELL, Robert S. , RUST, Camron B. , LUU, Han S. , ONG, Leslie A. , HILDESHEIM, Gur
发明人： RAIKIN, Shlomo , HAMAMA, Oren , CHAPPELL, Robert S. , RUST, Camron B. , LUU, Han S. , ONG, Leslie A. , HILDESHEIM, Gur
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , Y02D10/13
摘要： An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.
摘要翻译：一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。

5. 发明申请

WO2018048582A1 DEFINING VIRTUALIZED PAGE ATTRIBUTES BASED ON GUEST PAGE ATTRIBUTES 审中-公开
标题翻译：基于访客页面属性定义虚拟化页面属性
公开(公告)号：WO2018048582A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/046812
申请日：2017-08-14
申请人： INTEL CORPORATION
发明人： NEIGER, Gilbert , PATEL, Baiju V. , HILDESHEIM, Gur , RAIS, Ron , ANDERSON, Andrew V. , BRANDT, Jason W. , DURHAM, David M. , HUNTLEY, Barry E. , SADE, Raanan , SAHITA, Ravi L. , SHANBHOGUE, Vedvyas , THIYAGARAJAH, Arumugam
IPC分类号： G06F9/455
CPC分类号： G06F12/1009 , G06F9/45545 , G06F9/45558 , G06F12/1441 , G06F12/145 , G06F12/1491 , G06F2009/45583 , G06F2009/45587 , G06F2212/151 , G06F2212/651
摘要： A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.
摘要翻译：处理系统包括处理核心以执行包括通信地耦合到处理核心的客户操作系统（OS）和存储器管理单元的虚拟机（VM），该VM包括存储设备以存储包括从与客户OS关联的客户物理地址（GPA）到存储器帧的标识符的映射的扩展页表项（EPTE），与以第一页面模式访问存储器帧关联的第一多个访问权限标志被由GPA标识的存储器页面的属性引用，以及第二多个访问权限标志与在由GPA标识的存储器页面的属性引用的第二页面模式下访问存储器帧相关联。

6. 发明申请

WO2017172297A1 APPARATUS AND METHOD FOR RE-EXECUTION OF FAULTING OPERATIONS 审中-公开
标题翻译：用于重新执行失败操作的装置和方法
公开(公告)号：WO2017172297A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/021108
申请日：2017-03-07
申请人： INTEL CORPORATION
发明人： HILDESHEIM, Gur , YANOVER, Igor , SHWARTSMAN, Stanislav , SADE, Raanan , RAIS, Ron
IPC分类号： G06F9/30 , G06F9/48
摘要： An apparatus and method are described for at-retirement re-execution of faulting operations. For example, one embodiment of a processor comprises: an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory; a first circuit to determine whether a current load/store operation is at retirement; a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not be dispatched at retirement.
摘要翻译：描述了用于退役重新执行错误操作的装置和方法。例如，处理器的一个实施例包括：无序引擎，用于调度和分派操作给执行单元，至少一些操作包括加载操作以加载来自系统存储器的数据并存储操作以将数据存储到系统内存; 确定当前加载/存储操作是否在退休的第一电路; 第二电路，用于在退役时已经调度加载/存储操作时使得日志记录电路和/或故障寄存器有效，其中在检测到与加载/存储操作相关联的故障状况时，与故障相关联的数据将是写入记录电路和/或故障寄存器，如果加载/存储操作在退役时未被调度，则第二电路使得记录电路和/或故障寄存器不活动。

7. 发明申请

WO2018044424A1 ENHANCE MEMORY ACCESS PERMISSION BASED ON PER-PAGE CURRENT PRIVILEGE LEVEL 审中-公开
标题翻译：基于每页电流特权级别提高存储器访问许可
公开(公告)号：WO2018044424A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/043388
申请日：2017-07-21
申请人： INTEL CORPORATION
发明人： HILDESHEIM, Gur , NEIGER, Gilbert , PATEL, Baiju V. , RAIS, Ron
IPC分类号： G06F12/14
摘要： A processing system includes a processing core and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store a page table entry (PTE) comprising a mapping from a virtual memory page referenced by an application running on the processing core to an identifier of a memory frame of a memory, a first plurality of access permission flags associated with accessing the memory frame under a first privilege mode, and a second plurality of access permission flags associated with accessing the memory under a second privilege mode.
摘要翻译：处理系统包括通信地耦合到处理核心的处理核心和存储器管理单元，所述处理核心和存储器管理单元包括存储设备以存储包括来自被引用的虚拟存储器页面的映射的页面表项（PTE）通过运行在所述处理核心上的应用到存储器的存储器帧的标识符来确定与在第一特权模式下访问所述存储器帧关联的第一多个访问权限标志和与访问所述第二多个访问权限标志相关联的第二多个访问权限标志，内存在第二特权模式下。

8. 发明申请

WO2014042747A1 CONCURRENT CONTROL FOR A PAGE MISS HANDLER 审中-公开
标题翻译：页面错误处理的并发控制
公开(公告)号：WO2014042747A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/048594
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： HILDESHEIM, Gur , TAN, Chang Kian , CHAPPELL, Robert S. , BHATIA, Rohit
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/10 , G06F12/1027 , G06F2212/1024 , G06F2212/651 , G06F2212/655 , G06F2212/681 , G06F2212/684
摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并从寻呼结构获得物理地址的对应部分，与第一步行者同时操作的第二步行者，用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应的线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼缓存中的逻辑。描述和要求保护其他实施例。

9. 发明申请

WO2014105122A1 ACCESS TYPE PROTECTION OF MEMORY RESERVED FOR USE BY PROCESSOR LOGIC 审中-公开
标题翻译：存储器访问类型保护由处理器逻辑使用
公开(公告)号：WO2014105122A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/045691
申请日：2013-06-13
申请人： INTEL CORPORATION
发明人： HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SHAFI, Hisham , BERENZON, Alex , STRONGIN, Geoffrey, S. , SORANI, Iris
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F12/1027 , G06F12/1441 , G06F12/145 , G06F2212/1052
摘要： A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.
摘要翻译：一方面的处理器包括操作模式检查逻辑，用于基于用于指示尝试的访问是否由片上处理器逻辑来确定是否允许尝试访问操作模式和访问类型受保护存储器的操作模式。访问类型检查逻辑是基于尝试访问操作模式和访问类型受保护的存储器的访问类型来确定是否允许尝试访问操作模式和访问类型受保护的存储器。保护逻辑与操作模式检查逻辑耦合，并与访问类型检查逻辑耦合。如果操作模式检查逻辑和访问类型检查逻辑中的至少一个确定不允许尝试访问，则保护逻辑是拒绝尝试访问操作模式和访问类型保护的存储器。

10. 发明公开

EP3504629A1 ENHANCE MEMORY ACCESS PERMISSION BASED ON PER-PAGE CURRENT PRIVILEGE LEVEL 有权
公开(公告)号：EP3504629A1
公开(公告)日：2019-07-03
申请号：EP17847142.1
申请日：2017-07-21
申请人： Intel Corporation
发明人： HILDESHEIM, Gur , NEIGER, Gilbert , PATEL, Baiju V. , RAIS, Ron
IPC分类号： G06F12/14

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