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1. 发明申请

WO2014004151A3 VIRTUAL MEMORY ADDRESS RANGE REGISTER 审中-公开
标题翻译：虚拟内存地址范围寄存器
公开(公告)号：WO2014004151A3
公开(公告)日：2014-03-13
申请号：PCT/US2013046169
申请日：2013-06-17
申请人： INTEL CORP , HILDESHEIM GUR , RAIKIN SHLOMO , ANATI ITTAI , GERZON GIDEON , SAVAGAONKAR UDAY , MCKEEN FRANCIS , ROZAS CARLOS , GOLDSMITH MICHAEL , DEWAN PRASHANT
发明人： HILDESHEIM GUR , RAIKIN SHLOMO , ANATI ITTAI , GERZON GIDEON , SAVAGAONKAR UDAY , MCKEEN FRANCIS , ROZAS CARLOS , GOLDSMITH MICHAEL , DEWAN PRASHANT
IPC分类号： G06F12/08
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口使用物理存储器地址访问系统存储器。地址转换硬件支持将虚拟存储器地址转换为物理存储器地址。虚拟内存地址被软件用来访问处理器的虚拟内存地址空间中的虚拟内存位置。虚拟内存地址比较硬件用于确定虚拟内存地址是否在虚拟内存地址范围内。

2. 发明申请

WO2014105167A1 APPARATUS AND METHOD FOR PAGE WALK EXTENSION FOR ENHANCED SECURITY CHECKS 审中-公开
标题翻译：用于增强安全检查的页面扩展的装置和方法
公开(公告)号：WO2014105167A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047423
申请日：2013-06-24
申请人： INTEL CORPORATION , HILDESHEIM, Gur , ANATI, Ittai , SHAIF, Hisham , RAIKIN, Shlomo , GERZON, Gideon , SAVAGAONKAR, Uday R. , ROZAS, Carlos V. , MCKEEN, Francis X. , GOLDSMITH, Michael A. , DEWAN, Prashant
发明人： HILDESHEIM, Gur , ANATI, Ittai , SHAIF, Hisham , RAIKIN, Shlomo , GERZON, Gideon , SAVAGAONKAR, Uday R. , ROZAS, Carlos V. , MCKEEN, Francis X. , GOLDSMITH, Michael A. , DEWAN, Prashant
IPC分类号： G06F21/78
CPC分类号： G06F12/145 , G06F12/084 , G06F12/1027 , G06F12/1483 , G06F21/53
摘要： An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.
摘要翻译：一种用于由处理器管理保护表的装置和方法。例如，根据本发明的一个实施例的处理器包括：保护表管理逻辑，用于管理保护表，所述保护表具有每个受保护页面的条目或存储器中的每组受保护页面; 其中保护表管理逻辑防止用户应用程序代码和操作系统程序代码直接访问保护表，但允许处理器直接访问。

3. 发明申请

WO2014004151A2 VIRTUAL MEMORY ADDRESS RANGE REGISTER 审中-公开
标题翻译：虚拟内存地址范围注册
公开(公告)号：WO2014004151A2
公开(公告)日：2014-01-03
申请号：PCT/US2013/046169
申请日：2013-06-17
申请人： INTEL CORPORATION , HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SAVAGAONKAR, Uday , MCKEEN, Francis , ROZAS, Carlos , GOLDSMITH, Michael , DEWAN, Prashant
发明人： HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SAVAGAONKAR, Uday , MCKEEN, Francis , ROZAS, Carlos , GOLDSMITH, Michael , DEWAN, Prashant
IPC分类号： G06F12/08
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

4. 发明申请

WO2013095467A1 A BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE 审中-公开
标题翻译：一个平衡的P-LRU树，一个“多个3”的方式高速缓存
公开(公告)号：WO2013095467A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066652
申请日：2011-12-21
申请人： INTEL CORPORATION , BASEL, Adi , HILDESHEIM, Gur , RAIKIN, Shlomo , CHAPPELL, Robert , KIM, Ho-Seop , BHATIA, Rohit
发明人： BASEL, Adi , HILDESHEIM, Gur , RAIKIN, Shlomo , CHAPPELL, Robert , KIM, Ho-Seop , BHATIA, Rohit
IPC分类号： G06F1/00
CPC分类号： G06F12/122 , G06F3/0604 , G06F12/00 , G06F12/0842 , G06F12/0864 , G06F12/124 , G06F12/125
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a "multiple of 3" number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N-1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a "multiple of 5" number of cache ways, and variations of the "multiple of 3" number of cache ways.
摘要翻译：根据本文公开的实施例，提供了用于实现用于“3”倍的方式高速缓存的平衡P-LRU树的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。在这样的实施例中，多个方式包括一个数量是三的倍数，而不是二的幂，并且其中多个方式被组织成多对。在这样的实施例中，装置还包括用于多个对中的每一对的单个位，其中每个单个位将用作表示相关联的方式的中间级决策节点和具有正好两个单独位的根级判定节点指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

5. 发明申请

WO2014105151A1 APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB) 审中-公开
标题翻译：多页翻页预处理缓存器（TLB）的设备和方法
公开(公告)号：WO2014105151A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046910
申请日：2013-06-20
申请人： INTEL CORPORATION , RAIKIN, Shlomo , HAMAMA, Oren , CHAPPELL, Robert S. , RUST, Camron B. , LUU, Han S. , ONG, Leslie A. , HILDESHEIM, Gur
发明人： RAIKIN, Shlomo , HAMAMA, Oren , CHAPPELL, Robert S. , RUST, Camron B. , LUU, Han S. , ONG, Leslie A. , HILDESHEIM, Gur
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , Y02D10/13
摘要： An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.
摘要翻译：一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。

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