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1. 发明申请

WO2016153662A1 PSEUDORANDOM BIT SEQUENCES IN AN INTERCONNECT 审中-公开
标题翻译：互连中的PSEUDORANDOM位比特序列
公开(公告)号：WO2016153662A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/018842
申请日：2016-02-22
申请人： INTEL CORPORATION
发明人： WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3183 , G06F13/42
CPC分类号： H04B3/46 , H04B3/32 , H04B3/487
摘要： In an example, a linear feedback shift register (LFSR) provides pseudorandom bit sequences (PRBSs) to an interconnect for training, testing, and scrambling purposes. The interconnect may include a state machine, with states including LOOPBACK, CENTERING, RECENTERING, and ACTIVE states, among others The interconnect is permitted to move from "CENTERING" to "LOOPBACK" via a sideband signal. In LOOPBACK, CENTERING, and RECENTERING, PRBSs are used for training and testing purposes to electrically characterize and test the interconnect, and to locate a midpoint for a reference voltage V ref. A unique, noncorrelated PRBS is provided to each lane, calculated using one common output bit. Multiple bits per lane may also be computed per clock cycle so that the LFSR can run at a slower clock rate than the interconnect. A selecting network may also be provided so that, as necessary, "victim," "aggressor," and "neutral" lanes may be provided for testing purposes.
摘要翻译：在一个示例中，线性反馈移位寄存器（LFSR）向用于训练，测试和加扰目的的互连提供伪随机比特序列（PRBS）。互连可以包括状态机，其中包括LOOPBACK，CENTERING，RECENTERING和ACTIVE状态等状态。互连允许经由边带信号从“CENTERING”移动到“LOOPBACK”。在LOOPBACK，CENTERING和RECENTERING中，PRBS用于训练和测试目的，用于电气表征和测试互连，并定位参考电压V ref的中点。使用一个公共输出位计算每个通道提供一个独特的，不相关的PRBS。每个时钟周期也可以计算每个通道的多个位，以便LFSR可以以比互连更慢的时钟速率运行。还可以提供选择网络，以便根据需要，可以为测试目的提供“受害者”，“侵略者”和“中立”通道。

2. 发明申请

WO2015099724A1 PCI EXPRESS ENHANCEMENTS 审中-公开
标题翻译： PCI EXPRESS增强
公开(公告)号：WO2015099724A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/077762
申请日：2013-12-26
申请人： INTEL CORPORATION , WU, Zuoguo , DAS SHARMA, Debendra , MAZUMDER, Md. Mohiuddin , BASTOLA, Subas , XIAO, Kai
发明人： WU, Zuoguo , DAS SHARMA, Debendra , MAZUMDER, Md. Mohiuddin , BASTOLA, Subas , XIAO, Kai
IPC分类号： G06F13/14
CPC分类号： H03M13/11 , G06F13/36 , G06F13/385 , G06F13/4068 , G06F13/4282 , G06F2213/0026
摘要： An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
摘要翻译：
做出链接将退出活动状态的标识，该链接包括多个通道。基于之前通过链路发送的数据为通道维护奇偶校验信息，并且在退出激活状态之前发送奇偶校验信息的指示。

3. 发明申请

WO2018063707A1 VOLTAGE MODULATED CONTROL LANE 审中-公开
标题翻译：电压调节控制LANE
公开(公告)号：WO2018063707A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049343
申请日：2017-08-30
申请人： INTEL CORPORATION
发明人： IYER, Venkatraman , WU, Zuoguo , WAGH, Mahesh
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4265 , G06F1/3253 , Y02D10/14 , Y02D10/151
摘要： A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal on a particular one of the plurality of lanes of the physical link, where the stream signal is to identify a type of the data on the one or more data lanes, the type is one of a plurality of different types supported by the particular component, and the stream signal is encoded through voltage amplitude modulation on the particular lane.
摘要翻译：为物理层逻辑提供计算组件以在包括多个通道的物理链路上接收数据，其中从物理链路的一个或多个数据通道上的特定组件接收数据。物理层进一步在物理链路的多个通道中的特定通道上接收流信号，其中流信号将识别一个或多个数据通道上的数据的类型，该类型是由特定部件支持的多种不同类型，并且流信号通过特定通道上的电压幅度调制进行编码。

4. 发明申请

WO2018004851A1 RLINK - ON-DIE INDUCTOR STRUCTURES TO IMPROVE SIGNALING 审中-公开
标题翻译： RLINK - 片上电感结构改善信号传输
公开(公告)号：WO2018004851A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/032940
申请日：2017-05-16
申请人： INTEL CORPORATION
发明人： ZHANG, Yu Amos , KIM, Jihwan , BALANKUTTY, Ajay , SRIRAMULU, Anupriya , MAZUMDER, MD. Mohiuddin , O'MAHONY, Frank , WU, Zuoguo , AYGUN, Kemal
IPC分类号： H01L23/62 , H01L49/02 , H01L23/64
摘要： Integrated circuit (IC) chip "on-die" inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.
摘要翻译：集成电路（IC）芯片“片上”（on-die）电感器结构（用于其制造的系统和方法）可以改善从数据信号电路到芯片的表面接触的信号传输。这样的电感器结构可以包括具有（1）电耦合到静电放电（ESD）电路的第二端和该电路的电容值的第一数据信号电感器，以及（2）电耦合到数据信号表面接触并达到该接触处的电容值; 以及第二数据信号电感器，其具有（1）电耦合到数据信号电路的第二端和该电路的电容值，（2）电耦合到第一数据信号电感器的第二端的第一端，以及 ESD电路的电容值。可以选择第一和第二电感器的电感值以消除电容值以改善信号传输。

5. 发明申请

WO2017200531A1 CHARACTERIZATION OF TRANSMISSION MEDIA 审中-公开
标题翻译：传输介质的特性
公开(公告)号：WO2017200531A1
公开(公告)日：2017-11-23
申请号：PCT/US2016/032820
申请日：2016-05-17
申请人： INTEL CORPORATION
发明人： XIE, Mayue , HU, Chengqing , GUO, Jong-Ru , WU, Zuoguo , GOYAL, Deepak
IPC分类号： G01N21/53 , G01M11/00
摘要： Disclosed herein are systems and methods for the characterization of transmission media, among other embodiments. For example, a system for characterizing a transmission medium may include: a waveform generator to generate an initial input waveform; waveform pre-processing circuitry to process the initial waveform to generate a processed input waveform for provision to the transmission medium, wherein the processed input waveform has a maximum amplitude greater than a maximum amplitude of the initial input waveform; and waveform output circuitry to display or store data representative of an initial output waveform, wherein the initial output waveform is output from the transmission medium as a reflection or transmission of the processed input waveform.
摘要翻译：这里公开了用于表征传输介质的系统和方法以及其他实施例。例如，用于表征传输介质的系统可以包括：波形生成器，用于生成初始输入波形; 波形预处理电路，用于处理初始波形以生成处理后的输入波形以提供给传输介质，其中处理后的输入波形具有大于初始输入波形的最大幅度的最大幅度; 以及波形输出电路，用于显示或存储表示初始输出波形的数据，其中初始输出波形作为处理过的输入波形的反射或传输而从传输媒体输出。

6. 发明申请

WO2017052575A1 EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE 审中-公开
标题翻译：扩展多媒体包装链接关闭包装
公开(公告)号：WO2017052575A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052160
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： DAS SHARMA, Debendra , WU, Zuoguo , WAGH, Mahesh , MAZUMDER, Mohiuddin M. , IYER, Venkatraman , MORRISS, Jeff C.
IPC分类号： G06F13/14 , G06F13/42
CPC分类号： G06F13/4265 , H01L25/0655 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
摘要： An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
摘要翻译：提供互连接口以使得能够通过包括多个通道的链路与脱包装置通信。互连接口的逻辑包括接收器逻辑，用于在链路的专用有效通道上接收来自非封包装置的有效信号，指示数据将到达多个通道中的多个专用数据通道，接收数据根据有效信号的到来从脱包装置采样的数据通道，并且在多个通道中的专用流通道上从脱包装置接收流信号。流信号对应于数据并指示数据的特定数据类型。特定数据类型可以是能够在链路的多个数据通道上接收的多种不同数据类型之一。

7. 发明申请

WO2016153660A1 MULTICHIP PACKAGE LINK 审中-公开
标题翻译：多媒体包链接
公开(公告)号：WO2016153660A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/018836
申请日：2016-02-22
申请人： INTEL CORPORATION
发明人： WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman , PASDAST, Gerald S. , BIRRITTELLA, Mark S. , AGARWAL, Ishwar , TEH, Lip Khoon , LIM, Su Wei , UPADHYAY, Anoop Kumar
IPC分类号： G06F13/42 , G06F13/14 , H04L12/701
CPC分类号： G06F13/4022 , G06F13/36 , G06F13/4068
摘要： A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h = n * p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k ≠ h , so that [ k / n ] hard IP blocks provide h = n * p available hard IP data lanes. In that case, h - k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.
摘要翻译：诸如逻辑PHY的片上系统可以被划分为具有固定路由的硬IP块和具有灵活路由的软IP块。每个硬IP块可以提供固定数量的车道。使用p硬IP块，其中每个块提供n个数据通道，h = n * p提供总硬IP数据通道。在系统设计要求k个总数据通道的情况下，k≠h可以使得[k / n]硬IP块提供h = n * p可用的硬IP数据通道。在这种情况下，可能禁用h-k通道。在发生通道反转的情况下，例如在硬IP和软IP之间，可以通过使用软IP内的多路复用器可编程开关来避免路由路由。

8. 发明申请

WO2016105631A1 DATA RATE DETECTION TO SIMPLIFY RETIMER LOGIC 审中-公开
标题翻译：数据速率检测，以简化退货逻辑
公开(公告)号：WO2016105631A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/054894
申请日：2015-10-09
申请人： INTEL CORPORATION
发明人： FROELICH, Daniel , WU, Zuoguo , SRIRAMULU, Anupriya
IPC分类号： G06F13/42
CPC分类号： H04L25/0262 , H04L25/03057 , H04L25/03343 , H04L25/03885
摘要： An apparatus is described herein. The apparatus comprises a physical layer (PHY), wherein analog circuitry of the physical layer is to determine a data rate. The apparatus also comprises a media access layer (MAC), wherein the media access layer is to receive the data rate from the physical layer.
摘要翻译：这里描述了一种装置。该装置包括物理层（PHY），其中物理层的模拟电路用于确定数据速率。该装置还包括媒体接入层（MAC），其中媒体接入层将从物理层接收数据速率。

9. 发明申请

WO2017112330A1 AUTOMATED DETECTION OF HIGH PERFORMANCE INTERCONNECT COUPLING 审中-公开
标题翻译：自动检测高性能互连耦合
公开(公告)号：WO2017112330A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063738
申请日：2016-11-25
申请人： INTEL CORPORATION
发明人： IYER, Venkatraman , WU, Zuoguo , OU, Jeffrey , IYER, Sitaraman
IPC分类号： G06F13/16
CPC分类号： G06F11/3051 , G06F1/263 , G06F13/4282
摘要： A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.
摘要翻译：第一设备的端口包括远程设备检测逻辑，用于在链路上检测远程第二设备，根据在端口处生成的电压来确定第二设备是否是直流电（DC ） - 耦合或交流（AC） - 耦合到链路，并且基于第二设备是DC耦合还是基于第二设备是DC耦合还是选择要在与第二设备的链路上进行通信的端口中应用的第一设置或第二设置中的一个或者交流耦合。

10. 发明申请

WO2017052661A1 MULTICHIP PACKAGE LINK ERROR DETECTION 审中-公开
标题翻译：多媒体封装链路错误检测
公开(公告)号：WO2017052661A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052509
申请日：2015-09-26
申请人： INTEL CORPORATION
发明人： IYER, Venkatraman , BLANKENSHIP, Robert G. , WAGH, Mahesh , WU, Zuoguo
IPC分类号： H04L1/00 , H04L1/20 , H04L29/06
CPC分类号： G06F11/1004 , G06F13/16 , G06F2213/16 , H04L1/00 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0075 , H04L1/1607 , H04L1/20 , H04L29/06 , H04L2001/0094
摘要： First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
摘要翻译：在物理链路的多个数据通道上接收第一数据，并且在标识第一数据的类型的流道上接收与第一数据相对应的流信号。在第一数据中识别特定类型的错误检测码的第一实例。在多个数据通道的至少一部分上接收第二数据，并且在标识第二数据的类型的流线路上接收对应于第二数据的流信号。在第二数据中识别特定类型的错误检测码的第二实例。流道是物理链路的另一条通道，在某些情况下，第二数据的类型与第一数据的类型不同。

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