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1. 发明申请

WO2022154831A1 LOGICAL PHYSICAL LAYER INTERFACE SPECIFICATION SUPPORT FOR PCIE 6.0, CXL 3.0, AND UPI 3.0 PROTOCOLS 审中-公开
公开(公告)号：WO2022154831A1
公开(公告)日：2022-07-21
申请号：PCT/US2021/050772
申请日：2021-09-17
申请人： INTEL CORPORATION
发明人： CHOUDHARY, Swadesh , WAGH, Mahesh , DAS SHARMA, Debendra
IPC分类号： G06F13/38 , G06F13/40 , G06F11/10
摘要： In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

2. 发明申请

WO2018017208A1 TECHNIQUES TO SUPPORT MULTIPLE INTERCONNECT PROTOCOLS FOR A COMMON SET OF INTERCONNECT CONNECTORS 审中-公开
标题翻译：用于为一组相互连接的连接器支持多种互连协议的技术
公开(公告)号：WO2018017208A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/037408
申请日：2017-06-14
申请人： INTEL CORPORATION
发明人： WAGH, Mahesh , MYERS, Mark S. , VAN DOREN, Stephen R. , ZIAKAS, Dimitrios , COURY, Bassam
IPC分类号： G06F13/42
摘要： Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.
摘要翻译：实施例通常可以指向用于确定多个连接器的配置的设备，系统，方法和技术，该配置将第一互连协议与多个连接器的第一子集相关联，以及与所述多个连接器的第二子集的第二互连协议，所述第一互连协议和所述第二互连协议是不同的互连协议，并且每个互连协议包括串行链路协议，相干链路协议和加速器链路协议中的一个，引起处理用于根据第一互连协议经由多个连接器的第一子集进行通信的数据，并且根据第二互连协议引起用于经由多个连接器的第二子集进行通信的数据的处理。

3. 发明申请

WO2017052661A1 MULTICHIP PACKAGE LINK ERROR DETECTION 审中-公开
标题翻译：多媒体封装链路错误检测
公开(公告)号：WO2017052661A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052509
申请日：2015-09-26
申请人： INTEL CORPORATION
发明人： IYER, Venkatraman , BLANKENSHIP, Robert G. , WAGH, Mahesh , WU, Zuoguo
IPC分类号： H04L1/00 , H04L1/20 , H04L29/06
CPC分类号： G06F11/1004 , G06F13/16 , G06F2213/16 , H04L1/00 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0075 , H04L1/1607 , H04L1/20 , H04L29/06 , H04L2001/0094
摘要： First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
摘要翻译：在物理链路的多个数据通道上接收第一数据，并且在标识第一数据的类型的流道上接收与第一数据相对应的流信号。在第一数据中识别特定类型的错误检测码的第一实例。在多个数据通道的至少一部分上接收第二数据，并且在标识第二数据的类型的流线路上接收对应于第二数据的流信号。在第二数据中识别特定类型的错误检测码的第二实例。流道是物理链路的另一条通道，在某些情况下，第二数据的类型与第一数据的类型不同。

4. 发明申请

WO2016105862A1 METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH-PERFORMANCE INTERCONNECT 审中-公开
标题翻译：方法，设备，高性能互连中心的系统
公开(公告)号：WO2016105862A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062855
申请日：2015-11-28
申请人： INTEL CORPORATION
发明人： WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman , PASDAST, Gerald S. , HINCK, Todd A. , LEE, David M. , LANKA, Narasimha R.
IPC分类号： G06F11/16 , G06F11/22 , G01R23/12 , G01R19/165
CPC分类号： H03K5/26 , G01R31/041 , G06F1/3296 , G06F13/4291 , H03K5/131 , H03L9/00
摘要： In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to "center" the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional "eye" phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a "victim" lane, with adjacent "aggressor" lanes having a complementary bit pattern.
摘要翻译：在一个示例中，公开了一种用于以高性能互连（HPI）为中心的系统和方法。当互连从休眠状态上电时，可能需要“中心”时钟信号，以确保在正确的时间读取数据。可以使用多相方法，其中第一相包括参考电压扫描以识别最佳参考电压。第二阶段包括相位扫描以识别最佳相位。第三扫描包括二维“眼”阶段，其中测试从前两次扫描得到的二维眼睛内的多个值。在每种情况下，最佳值是导致多个通道中最小位错误的值。在一个示例中，第二和第三阶段以软件执行，并且可以包括测试“受害者”通道，具有具有互补位模式的相邻“侵略者”通道。

5. 发明申请

WO2018063740A1 LINK-PHYSICAL LAYER INTERFACE ADAPTER 审中-公开
标题翻译：链路物理层接口适配器
公开(公告)号：WO2018063740A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049824
申请日：2017-09-01
申请人： INTEL CORPORATION
发明人： IYER, Venkatraman , WAGH, Mahesh , HALLECK, William R. , SHAH, Rahul R.
IPC分类号： G06F13/42
CPC分类号： G06F13/4068 , G06F13/36 , G06F13/4022 , G06F13/4027 , G06F13/4265
摘要： An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.
摘要翻译：用于识别来自第一通信协议的第一链路层到物理层（LL-PHY）接口的指示第一协议的物理层准备好接受的第一就绪信号的接口适配器链路层数据。接口适配器生成与第二通信协议的第二LL-PHY接口兼容的第二就绪信号，以使链路层数据根据预定延迟从第二通信协议的链路层发送。生成与第一LL-PHY接口兼容的第三就绪信号，以向第一通信协议的物理层指示链路层数据将被发送。接口适配器使用移位寄存器来根据预定义的延迟将链路层数据传递到物理层。

6. 发明申请

WO2017112198A1 ARCHITECTURE FOR SOFTWARE DEFINED INTERCONNECT SWITCH 审中-公开
标题翻译：用于软件定义的互连开关的体系结构
公开(公告)号：WO2017112198A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062968
申请日：2016-11-20
申请人： INTEL CORPORATION
发明人： HARRIMAN, David J. , KULKARNI, Manjari , PETHE, Akshay G. , STALLEY, Sean O. , WAGH, Mahesh , DAS SHARMA, Debendra
IPC分类号： G06F15/173
CPC分类号： G06F13/4022 , G06F13/36 , G06F13/4282
摘要： An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a 5 control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.
摘要翻译：提供互连交换机，其包括可执行以促进基于外围组件互连高速（PCIe）的互连的交换逻辑，并且还包括嵌入交换机中的控制主机以提供一个或多个增强的路由能力。控制主机包括处理器设备，存储器以及可由处理器设备执行的软件，以处理在交换机的一个或多个端口处接收到的流量，以重定向至少一部分流量以提供一个或多个增强的路由能力。 p>

7. 发明申请

WO2017052663A1 VALID LANE TRAINING 审中-公开
标题翻译：有效的训练
公开(公告)号：WO2017052663A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052512
申请日：2015-09-26
申请人： INTEL CORPORATION
发明人： IYER, Venkatraman , TEH, Lip, Khoon , WAGH, Mahesh , WU, Zuoguo , HAMID, Azydee , PASDAST, Gerald, S.
IPC分类号： G06F13/42 , G06F13/38 , G06F13/14
CPC分类号： G06F13/40
摘要： One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.
摘要翻译：在包括至少一个有效车道和多个数据车道的物理链路的多个车道上接收一个或多个链路训练信号，包括链路训练模式的实例。使用链路训练信号将多个车道一起训练，以使有效车道的采样与多个数据车道的采样同步。在活动链路状态期间，输入有效链路状态并在有效通道上接收到有效信号。有效信号包括保持在定义的第一持续时间的值的信号，并且指示将在第一持续时间之后的第二限定持续时间内在多个数据通道上接收数据。在活动链路状态期间，将在第二定义的持续时间期间在多个数据通道上接收数据。

8. 发明申请

WO2016105953A1 A METHOD, APPARATUS, SYSTEM FOR EMBEDDED STREAM LANES IN A HIGH-PERFORMANCE INTERCONNECT 审中-公开
标题翻译：高性能互连嵌入式流域的方法，装置，系统
公开(公告)号：WO2016105953A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/064862
申请日：2015-12-10
申请人： INTEL CORPORATION
发明人： WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman
IPC分类号： H04L12/40 , H04L12/801 , G06F13/14 , G06F13/38
CPC分类号： G06F13/4068 , G06F13/4265 , H04L12/40
摘要： In an example, a high-performance interconnect (HPI) is provisioned without a separate stream lane. To provide equivalent functionality, stream lane data are provided within data lines during idle periods. Because one stream lane may be provided per 20 data lanes, elimination of the stream lane saves approximately 5% of area. In a pre-data time, the 20 data lanes may be brought high from midrail to represent one species of data (for example, Intel® in-die interconnect (IDI)), and brought low to represent a second species of data (for example, Intel® on-chip system fabric (IOSF)). To represent additional species of data, such as link control packets (LCPs) for example, lanes can be divided into two or more groups, and a single bit can be encoded into each group. LCP can also be encoded into a post-data time, for example by ceasing flit traffic and manipulating a "VALID" lane from midrail to 0 or 1.
摘要翻译：在一个示例中，高性能互连（HPI）被提供而没有单独的流线。为了提供等效的功能，在空闲周期内在数据线内提供流道数据。因为每20条数据通道可以提供一条流道，所以流线路的消除节省了大约5％的面积。在预数据时间内，20个数据通道可能会从中段带来很高的，以表示一种数据（例如，英特尔®芯片间互连（IDI）），并带来了低的代表第二种数据（对于例如英特尔®片上系统架构（IOSF））。为了表示例如链路控制分组（LCP）的附加数据种类，可以将通道划分为两个或更多个组，并且可以将单个比特编码到每个组中。 LCP也可以被编码成后数据时间，例如通过停止飞行交通并且操纵从中途到0或1的“有效”通道。

9. 发明申请

WO2016039791A1 SERIAL SIDEBAND SIGNALING LINK 审中-公开
标题翻译：串行信号链路
公开(公告)号：WO2016039791A1
公开(公告)日：2016-03-17
申请号：PCT/US2014/072389
申请日：2014-12-24
申请人： INTEL CORPORATION
发明人： PETHE, Akshay , WAGH, Mahesh , HARRIMAN, David , LIM, Su Wei , DAS SHARMA, Debendra , FROELICH, Daniel , IYER, Venkatraman , JAUSSI, James , WU, Zuoguo
IPC分类号： G06F13/14
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4027 , G06F2213/0042 , G06F2213/4002
摘要： Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.
摘要翻译：本文描述了嵌入式高速串行接口方法的技术。这些技术包括用于边带信令的装置，包括第一串行边带链路模块和第二串行边带链路模块。第一串行边带链路模块是经由第一信令通道将分组从上游端口传播到下游端口，并且第二串行边带链路模块通过第二信令通道将分组从下游端口传播到上游端口。

10. 发明申请

WO2019005391A1 TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM INTERCONNECTS 审中-公开
公开(公告)号：WO2019005391A1
公开(公告)日：2019-01-03
申请号：PCT/US2018/035034
申请日：2018-05-30
申请人： INTEL CORPORATION
发明人： SUNDARARAMAN, Ramacharan , WAGH, Mahesh , SOLTIS, Don , DAS SHARMA, Debendra , JEN, Michelle , VAN DOREN, Stephen , MYERS, Mark
IPC分类号： G06F13/42
摘要： Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component having a plurality of on-package devices, at least one on-package interconnect between at least a portion of the plurality of on-package devices, at least one off-package interconnect between the component and at least one off-package device, and interface logic, at least a portion of the interface logic comprised in hardware, the interface logic to determine data to be communicated, route the data using a multi-interconnect protocol via the at least one on-package interconnect for communication between the plurality of on-package devices, and route the data using a standard interconnect protocol via the at least one off-package interconnect for communication between the plurality of on-package devices and the at least one off-package. Other embodiments are described.

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