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1. 发明申请

WO2018004851A1 RLINK - ON-DIE INDUCTOR STRUCTURES TO IMPROVE SIGNALING 审中-公开
标题翻译： RLINK - 片上电感结构改善信号传输
公开(公告)号：WO2018004851A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/032940
申请日：2017-05-16
申请人： INTEL CORPORATION
发明人： ZHANG, Yu Amos , KIM, Jihwan , BALANKUTTY, Ajay , SRIRAMULU, Anupriya , MAZUMDER, MD. Mohiuddin , O'MAHONY, Frank , WU, Zuoguo , AYGUN, Kemal
IPC分类号： H01L23/62 , H01L49/02 , H01L23/64
摘要： Integrated circuit (IC) chip "on-die" inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.
摘要翻译：集成电路（IC）芯片“片上”（on-die）电感器结构（用于其制造的系统和方法）可以改善从数据信号电路到芯片的表面接触的信号传输。这样的电感器结构可以包括具有（1）电耦合到静电放电（ESD）电路的第二端和该电路的电容值的第一数据信号电感器，以及（2）电耦合到数据信号表面接触并达到该接触处的电容值; 以及第二数据信号电感器，其具有（1）电耦合到数据信号电路的第二端和该电路的电容值，（2）电耦合到第一数据信号电感器的第二端的第一端，以及 ESD电路的电容值。可以选择第一和第二电感器的电感值以消除电容值以改善信号传输。

2. 发明申请

WO2020068206A1 A DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED DELAY-LOCKED LOOP (DLL) 审中-公开
公开(公告)号：WO2020068206A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/039061
申请日：2019-06-25
申请人： INTEL CORPORATION
发明人： MARTIN, Aaron , CHENG, Roger , VENKATRAMANI, Hari , DOUR, Navneet , MANSURI, Mozhgan , CASPER, Bryan , O'MAHONY, Frank , BALAMURUGAN, Ganesh , BALANKUTTY, Ajay , ZHOU, Kuan , TIRUMALAI, Sridhar , VENKATARAMANA, Krishnamurthy , THOMAS, Alex , NGUYEN, Quoc
IPC分类号： H03K5/156 , G05F1/575 , H03L7/081 , G06F1/08
摘要： An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

3. 发明申请

WO2013074076A1 MACRO-TRANSISTOR DEVICES 审中-公开
标题翻译：宏器件设备
公开(公告)号：WO2013074076A1
公开(公告)日：2013-05-23
申请号：PCT/US2011/060652
申请日：2011-11-14
申请人： INTEL CORPORATION , HYVONEN, Sami , RIZK, Jad B. , O'MAHONY, Frank
发明人： HYVONEN, Sami , RIZK, Jad B. , O'MAHONY, Frank
IPC分类号： H01L27/00 , H01L21/768
CPC分类号： H01L27/0886 , H01L27/088 , H01L27/1211 , H01L29/42376 , H01L29/66181 , H01L29/785 , H01L29/93 , H01L29/94 , H03L7/099
摘要： Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.
摘要翻译：公开了宏观晶体管结构。在一些情况下，宏晶体管结构具有与长沟道晶体管类似的端子和性质相同的数量，但适用于深亚微米技术深亚微米工艺节点中的模拟电路。宏晶体管结构可以例如通过串联构造和布置的多个晶体管实现，并且其栅极连接在一起，这里通常称为晶体管堆叠。堆叠内的一个或多个串联晶体管可以用多个并联晶体管实现和/或可以具有不同于堆叠中其它晶体管的阈值电压的阈值电压。或者或另外，宏晶体管内的一个或多个串联晶体管可以被静态或动态地控制，以调整宏晶体管的性能特性。宏晶体管可用于许多电路，例如变容二极管，VCO，PLL和可调谐电路。

4. 发明申请

WO2015076789A1 CLOCK CALIBRATION USING ASYNCHRONOUS DIGITAL SAMPLING 审中-公开
标题翻译：使用异步数字采样的时钟校准
公开(公告)号：WO2015076789A1
公开(公告)日：2015-05-28
申请号：PCT/US2013/070824
申请日：2013-11-19
申请人： INTEL CORPORATION
发明人： BALAMURUGAN, Ganesh , MANSURI, Mozhgan , HYVONEN, Sami , CASPER, Bryan, K. , O'MAHONY, Frank
IPC分类号： H03L7/00 , H04L7/00
CPC分类号： H03L7/00 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03K5/1565 , H03L7/08 , H04B1/04 , H04L25/03
摘要： Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.
摘要翻译：描述了一种装置，其包括：异步时钟发生器，用于产生异步时钟信号; 数字采样器，用于使用异步时钟信号对信号进行采样; 用于接收差分输入时钟并产生差分输出时钟的占空比校正器（DCC），其中所述数字采样器从所述差分输出时钟采样至少一个输出时钟; 以及计数器来计数数字采样器的输出，并向DCC提供控制以调整差分输出时钟的占空比。

5. 发明申请

WO2013147839A1 ON-DIE ALL-DIGITAL DELAY MEASUREMENT CIRCUIT 审中-公开
标题翻译：全数字数字延时测量电路
公开(公告)号：WO2013147839A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031408
申请日：2012-03-30
申请人： INTEL CORPORATION , O'MAHONY, Frank , CASPER, Bryan K. , MANSURI, Mozhgan
发明人： O'MAHONY, Frank , CASPER, Bryan K. , MANSURI, Mozhgan
IPC分类号： G01R23/175 , H03K5/13 , H03L7/081
CPC分类号： G01R31/31725 , G01R25/08 , G01R31/31726 , G04F10/005 , H03K2005/00052
摘要： An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.
摘要翻译：在集成电路（IC）芯片上构造的全数字延迟测量电路（DMC）表征了也在IC芯片上构造的诸如全相位旋转内插器的时钟电路。片上全数字DMC产生与两个时钟之间的相对延迟成比例的数字输出值，归一化为两个时钟的时钟周期。

6. 发明授权

EP2831603B1 ON-DIE ALL-DIGITAL DELAY MEASUREMENT CIRCUIT 有权
公开(公告)号：EP2831603B1
公开(公告)日：2019-11-13
申请号：EP12872863.1
申请日：2012-03-30
申请人： Intel Corporation
发明人： O'MAHONY, Frank , CASPER, Bryan K. , MANSURI, Mozhgan
IPC分类号： G01R23/175 , H03K5/00 , H03L7/081 , G04F10/00 , G01R31/317 , G01R25/08

7. 发明公开

EP3072239A1 CLOCK CALIBRATION USING ASYNCHRONOUS DIGITAL SAMPLING 审中-公开
标题翻译： UHRENKALIBRIERUNG麻省理工大学毕业生ABTASTUNG
公开(公告)号：EP3072239A1
公开(公告)日：2016-09-28
申请号：EP13897939.8
申请日：2013-11-19
申请人： Intel Corporation
发明人： BALAMURUGAN, Ganesh , MANSURI, Mozhgan , HYVONEN, Sami , CASPER, Bryan K. , O'MAHONY, Frank
IPC分类号： H03L7/00 , H04L7/00
CPC分类号： H03L7/00 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03K5/1565 , H03L7/08 , H04B1/04 , H04L25/03
摘要： Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.
摘要翻译：描述了一种装置，包括：异步时钟发生器，用于产生异步时钟信号; 数字采样器，用于使用异步时钟信号对信号进行采样; 占空比校正器（DCC），用于接收差分输入时钟并产生差分输出时钟，其中数字采样器从差分输出时钟采样至少一个输出时钟; 以及计数器对数字采样器的输出进行计数，并向DCC提供控制以调整差分输出时钟的占空比。

8. 发明公开

EP2831603A1 ON-DIE ALL-DIGITAL DELAY MEASUREMENT CIRCUIT 有权
标题翻译：全数字延迟测量电路上的芯片
公开(公告)号：EP2831603A1
公开(公告)日：2015-02-04
申请号：EP12872863.1
申请日：2012-03-30
申请人： Intel Corporation
发明人： O'MAHONY, Frank , CASPER, Bryan K. , MANSURI, Mozhgan
IPC分类号： G01R23/175 , H03K5/13 , H03L7/081
CPC分类号： G01R31/31725 , G01R25/08 , G01R31/31726 , G04F10/005 , H03K2005/00052
摘要： An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.

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