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1. 发明申请

WO2018004851A1 RLINK - ON-DIE INDUCTOR STRUCTURES TO IMPROVE SIGNALING 审中-公开
标题翻译： RLINK - 片上电感结构改善信号传输
公开(公告)号：WO2018004851A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/032940
申请日：2017-05-16
申请人： INTEL CORPORATION
发明人： ZHANG, Yu Amos , KIM, Jihwan , BALANKUTTY, Ajay , SRIRAMULU, Anupriya , MAZUMDER, MD. Mohiuddin , O'MAHONY, Frank , WU, Zuoguo , AYGUN, Kemal
IPC分类号： H01L23/62 , H01L49/02 , H01L23/64
摘要： Integrated circuit (IC) chip "on-die" inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.
摘要翻译：集成电路（IC）芯片“片上”（on-die）电感器结构（用于其制造的系统和方法）可以改善从数据信号电路到芯片的表面接触的信号传输。这样的电感器结构可以包括具有（1）电耦合到静电放电（ESD）电路的第二端和该电路的电容值的第一数据信号电感器，以及（2）电耦合到数据信号表面接触并达到该接触处的电容值; 以及第二数据信号电感器，其具有（1）电耦合到数据信号电路的第二端和该电路的电容值，（2）电耦合到第一数据信号电感器的第二端的第一端，以及 ESD电路的电容值。可以选择第一和第二电感器的电感值以消除电容值以改善信号传输。

2. 发明申请

WO2022132254A1 ANALOG EQUALIZATION WITH PEAKING AND SLOPE CONTROL 审中-公开
公开(公告)号：WO2022132254A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/049897
申请日：2021-09-10
申请人： INTEL CORPORATION
发明人： LEVIN, Itamar , GRAFI, Tali Warshavsky , CUSMAI, Marco , BALANKUTTY, Ajay , SHIVA KIRAN, Fnu , COHEN, Ariel
IPC分类号： H04L25/03
摘要： An apparatus comprising at least one medium to transport a signal and an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises independently tunable parameters including a peak frequency gain and a mid-range frequency response slope. The independently tunable parameters of the analog equalization circuit include a low frequency de-emphasis amount.

3. 发明申请

WO2020068206A1 A DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED DELAY-LOCKED LOOP (DLL) 审中-公开
公开(公告)号：WO2020068206A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/039061
申请日：2019-06-25
申请人： INTEL CORPORATION
发明人： MARTIN, Aaron , CHENG, Roger , VENKATRAMANI, Hari , DOUR, Navneet , MANSURI, Mozhgan , CASPER, Bryan , O'MAHONY, Frank , BALAMURUGAN, Ganesh , BALANKUTTY, Ajay , ZHOU, Kuan , TIRUMALAI, Sridhar , VENKATARAMANA, Krishnamurthy , THOMAS, Alex , NGUYEN, Quoc
IPC分类号： H03K5/156 , G05F1/575 , H03L7/081 , G06F1/08
摘要： An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

4. 发明公开

EP4264896A1 ANALOG EQUALIZATION WITH PEAKING AND SLOPE CONTROL 审中-实审
公开(公告)号：EP4264896A1
公开(公告)日：2023-10-25
申请号：EP21907371.5
申请日：2021-09-10
申请人： Intel Corporation
发明人： LEVIN, Itamar , GRAFI, Tali Warshavsky , CUSMAI, Marco , BALANKUTTY, Ajay , SHIVA KIRAN, Fnu , COHEN, Ariel
IPC分类号： H04L25/03

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