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1. 发明申请

WO2017052663A1 VALID LANE TRAINING 审中-公开
标题翻译：有效的训练
公开(公告)号：WO2017052663A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052512
申请日：2015-09-26
申请人： INTEL CORPORATION
发明人： IYER, Venkatraman , TEH, Lip, Khoon , WAGH, Mahesh , WU, Zuoguo , HAMID, Azydee , PASDAST, Gerald, S.
IPC分类号： G06F13/42 , G06F13/38 , G06F13/14
CPC分类号： G06F13/40
摘要： One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.
摘要翻译：在包括至少一个有效车道和多个数据车道的物理链路的多个车道上接收一个或多个链路训练信号，包括链路训练模式的实例。使用链路训练信号将多个车道一起训练，以使有效车道的采样与多个数据车道的采样同步。在活动链路状态期间，输入有效链路状态并在有效通道上接收到有效信号。有效信号包括保持在定义的第一持续时间的值的信号，并且指示将在第一持续时间之后的第二限定持续时间内在多个数据通道上接收数据。在活动链路状态期间，将在第二定义的持续时间期间在多个数据通道上接收数据。

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