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1. 发明申请

WO2020068239A1 DUAL POWER I/O TRANSMITTER 审中-公开
公开(公告)号：WO2020068239A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/039976
申请日：2019-06-28
申请人： INTEL CORPORATION
发明人： VENKATRAM, Hariprasath , MOSTOFA, Mohammed , INTI, Rajesh , CHENG, Roger K. , MARTIN, Aaron , MOZAK, Christopher , KAPPANGANTULA, Pavan Kumar , YANG, Hsien-Pao , MANSURI, Mozhgan , JAUSSI, James , SRIDHARAN, Harishankar
IPC分类号： G11C11/4074 , G11C5/14
摘要： An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

2. 发明申请

WO2004098048A2 AMPLIFIER APPARATUS, METHOD, AND SYSTEM 审中-公开
标题翻译：放大器装置，方法和系统
公开(公告)号：WO2004098048A2
公开(公告)日：2004-11-11
申请号：PCT/US2004/009031
申请日：2004-03-24
申请人： INTEL CORPORATION
发明人： JAUSSI, James
IPC分类号： H03F3/45
CPC分类号： H03G1/0088 , H03F3/45183 , H03F2203/45466 , H03F2203/45641 , H03G1/0023
摘要： An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.
摘要翻译：放大器包括多个增益范围。增益范围可以通过电加载或去除负载设备来设置。

3. 发明申请

WO2005027445A1 CALIBRATION OF SCALE FACTOR IN ADAPTATIVE EQUALIZERS 审中-公开
标题翻译：量化因子在适应均衡中的校准
公开(公告)号：WO2005027445A1
公开(公告)日：2005-03-24
申请号：PCT/US2004/029055
申请日：2004-09-03
申请人： INTEL CORPORATION
发明人： BALAMURUGAN, Ganesh , CASPER, Bryan , JAUSSI, James , MOONEY, Stephen
IPC分类号： H04L25/03
CPC分类号： H04L25/03038 , H03H21/0001 , H03H2021/0065 , H04L2025/03477
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h ( t + 1) = h ( t ) + µ [sgn { d ( t )} - sgn { z ( t ) - Kd ( t )}]sgn {x( t )} , where h ( t ) is the filter vector representing the filter taps of the FIR filter, x( t ) is the data vector representing present and past samples of the received data x ( t ), d ( t ) is the desired data used for training, z ( t ) is the output of the FIR filter, µ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
摘要翻译：用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：h（t + 1）= h（t）+μ [sgn {d（t）} - sgn {z（t）-Kd（t）}] sgn {x（t）}，其中h（t）是表示FIR滤波器的滤波器抽头的滤波器向量， t）是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，μ确定存储器或窗口适应的大小，K是考虑通信信道，接收机和均衡器的实际限制的比例因子。此外，提供了用于校准比例因子K的过程和电路结构。

4. 发明申请

WO2004100357A2 LARGE GAIN-BANDWIDTH AMPLIFIER, METHOD, AND SYSTEM 审中-公开
标题翻译：大型增益放大器
公开(公告)号：WO2004100357A2
公开(公告)日：2004-11-18
申请号：PCT/US2004/008921
申请日：2004-03-24
申请人： INTEL CORPORATION
发明人： JAUSSI, James , KENNEDY, Joseph , MOONEY, Stephen
IPC分类号： H03F3/45
CPC分类号： H03F1/486 , H03F3/4521 , H03F2200/36 , H03K19/01759 , H03K19/018592
摘要： An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.
摘要翻译：放大器包括多个阶段。多级放大器的早期阶段具有较低的增益并保持带宽。

5. 发明申请

WO2020060543A1 ULTRA-HIGH DATA RATE DIGITAL MM-WAVE TRANSMITTER WITH ENERGY EFFICIENT SPECTRAL FILTERING 审中-公开
公开(公告)号：WO2020060543A1
公开(公告)日：2020-03-26
申请号：PCT/US2018/051667
申请日：2018-09-19
申请人： INTEL CORPORATION
发明人： CASPER, Bryan , JAUSSI, James , THAKKAR, Chintan , SHOPOV, Stefan
IPC分类号： H04L27/36 , H03F3/193 , H03F3/21 , H03F3/24 , H04L25/03
摘要： A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.

6. 发明申请

WO2016039791A1 SERIAL SIDEBAND SIGNALING LINK 审中-公开
标题翻译：串行信号链路
公开(公告)号：WO2016039791A1
公开(公告)日：2016-03-17
申请号：PCT/US2014/072389
申请日：2014-12-24
申请人： INTEL CORPORATION
发明人： PETHE, Akshay , WAGH, Mahesh , HARRIMAN, David , LIM, Su Wei , DAS SHARMA, Debendra , FROELICH, Daniel , IYER, Venkatraman , JAUSSI, James , WU, Zuoguo
IPC分类号： G06F13/14
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4027 , G06F2213/0042 , G06F2213/4002
摘要： Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.
摘要翻译：本文描述了嵌入式高速串行接口方法的技术。这些技术包括用于边带信令的装置，包括第一串行边带链路模块和第二串行边带链路模块。第一串行边带链路模块是经由第一信令通道将分组从上游端口传播到下游端口，并且第二串行边带链路模块通过第二信令通道将分组从下游端口传播到上游端口。

7. 发明申请

WO2005027446A1 ADAPTIVE EQUALIZATION USING A CONDITIONAL UPDATE SIGN-SIGN LEAST MEAN SQUARE ALGORITHM 审中-公开
标题翻译：使用条件更新的自适应均衡签名最小均方算法
公开(公告)号：WO2005027446A1
公开(公告)日：2005-03-24
申请号：PCT/US2004/029175
申请日：2004-09-08
申请人： INTEL CORPORATION , BALAMURUGAN, Ganesh , CASPER, Bryan , JAUSSI, James , MOONEY, Stephen
发明人： BALAMURUGAN, Ganesh , CASPER, Bryan , JAUSSI, James , MOONEY, Stephen
IPC分类号： H04L25/03
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065 , H04L25/03038 , H04L25/03885 , H04L2025/03477 , H04L2025/03617
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: (I), where (II) is the filter vector representing the filter taps of the FIR filter, (III) is the data vector representing present and past samples of the received data x (t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, µ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K .
摘要翻译：用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：（I），其中（II）是表示 FIR滤波器的滤波器抽头（III）是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z（t）是 FIR滤波器，μ确定适配的存储器或窗口大小，K是考虑通信信道，接收机和均衡器的实际限制的比例因子。此外，提供了用于校准比例因子K的过程和电路结构。

8. 发明授权

EP3191969B1 SERIAL SIDEBAND SIGNALING LINK 有权
公开(公告)号：EP3191969B1
公开(公告)日：2020-11-11
申请号：EP14901804.6
申请日：2014-12-24
申请人： Intel Corporation
发明人： PETHE, Akshay , WAGH, Mahesh , HARRIMAN, David , LIM, Su Wei , DAS SHARMA, Debendra , FROELICH, Daniel , IYER, Venkatraman , JAUSSI, James , WU, Zuoguo
IPC分类号： G06F13/14 , G06F13/38 , G06F13/40 , G06F13/42

9. 发明公开

EP3191969A1 SERIAL SIDEBAND SIGNALING LINK 审中-公开
标题翻译：串行边带信号链接
公开(公告)号：EP3191969A1
公开(公告)日：2017-07-19
申请号：EP14901804.6
申请日：2014-12-24
申请人： Intel Corporation
发明人： PETHE, Akshay , WAGH, Mahesh , HARRIMAN, David , LIM, Su Wei , DAS SHARMA, Debendra , FROELICH, Daniel , IYER, Venkatraman , JAUSSI, James , WU, Zuoguo
IPC分类号： G06F13/14
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4027 , G06F2213/0042 , G06F2213/4002
摘要： Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.
摘要翻译：这里描述了用于嵌入式高速串行接口方法的技术。该技术包括用于边带信令的装置，该装置包括第一串行边带链路模块和第二串行边带链路模块。第一串行边带链路模块是经由第一信令通道将分组从上游端口传播到下游端口，并且第二串行边带链路模块是经由第二信令通道将分组从下游端口传播到上游端口。

10. 发明公开

EP1618652A2 LARGE GAIN-BANDWITH AMPLIFIER 审中-公开
标题翻译：与大增益带宽放大器
公开(公告)号：EP1618652A2
公开(公告)日：2006-01-25
申请号：EP04760497.0
申请日：2004-03-24
申请人： INTEL CORPORATION
发明人： JAUSSI, James , KENNEDY, Joseph , MOONEY, Stephen
IPC分类号： H03F3/45 , H03F1/48 , H03K19/0175
CPC分类号： H03F1/486 , H03F3/4521 , H03F2200/36 , H03K19/01759 , H03K19/018592
摘要： An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.

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