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1. 发明申请

WO2016148804A1 HIGH SPEED RECEIVER WITH ONE-HOT DECISION FEEDBACK EQUALIZER 审中-公开
标题翻译：高速接收器，具有一个单独的反馈反馈均衡器
公开(公告)号：WO2016148804A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/017405
申请日：2016-02-10
申请人： INTEL CORPORATION
发明人： VENKATRAM, Hariprasath , HYVONEN, Sami , MUSAH, Tawfiq , CASPER, Bryan K.
IPC分类号： H04L25/03 , H04L7/033
CPC分类号： H04L25/03057 , H04L7/0062 , H04L7/033 , H04L7/0334 , H04L25/03878
摘要： Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1-hot encoded data.
摘要翻译：描述了一种装置，包括：放大器; 第一组采样器，用于根据时钟信号对从放大器输出的数据进行采样，该采样器组用于产生输出; 以及将第一组采样器的输出转换为1个热编码数据的转换器。

2. 发明申请

WO2013074076A1 MACRO-TRANSISTOR DEVICES 审中-公开
标题翻译：宏器件设备
公开(公告)号：WO2013074076A1
公开(公告)日：2013-05-23
申请号：PCT/US2011/060652
申请日：2011-11-14
申请人： INTEL CORPORATION , HYVONEN, Sami , RIZK, Jad B. , O'MAHONY, Frank
发明人： HYVONEN, Sami , RIZK, Jad B. , O'MAHONY, Frank
IPC分类号： H01L27/00 , H01L21/768
CPC分类号： H01L27/0886 , H01L27/088 , H01L27/1211 , H01L29/42376 , H01L29/66181 , H01L29/785 , H01L29/93 , H01L29/94 , H03L7/099
摘要： Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.
摘要翻译：公开了宏观晶体管结构。在一些情况下，宏晶体管结构具有与长沟道晶体管类似的端子和性质相同的数量，但适用于深亚微米技术深亚微米工艺节点中的模拟电路。宏晶体管结构可以例如通过串联构造和布置的多个晶体管实现，并且其栅极连接在一起，这里通常称为晶体管堆叠。堆叠内的一个或多个串联晶体管可以用多个并联晶体管实现和/或可以具有不同于堆叠中其它晶体管的阈值电压的阈值电压。或者或另外，宏晶体管内的一个或多个串联晶体管可以被静态或动态地控制，以调整宏晶体管的性能特性。宏晶体管可用于许多电路，例如变容二极管，VCO，PLL和可调谐电路。

3. 发明申请

WO2015076789A1 CLOCK CALIBRATION USING ASYNCHRONOUS DIGITAL SAMPLING 审中-公开
标题翻译：使用异步数字采样的时钟校准
公开(公告)号：WO2015076789A1
公开(公告)日：2015-05-28
申请号：PCT/US2013/070824
申请日：2013-11-19
申请人： INTEL CORPORATION
发明人： BALAMURUGAN, Ganesh , MANSURI, Mozhgan , HYVONEN, Sami , CASPER, Bryan, K. , O'MAHONY, Frank
IPC分类号： H03L7/00 , H04L7/00
CPC分类号： H03L7/00 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03K5/1565 , H03L7/08 , H04B1/04 , H04L25/03
摘要： Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.
摘要翻译：描述了一种装置，其包括：异步时钟发生器，用于产生异步时钟信号; 数字采样器，用于使用异步时钟信号对信号进行采样; 用于接收差分输入时钟并产生差分输出时钟的占空比校正器（DCC），其中所述数字采样器从所述差分输出时钟采样至少一个输出时钟; 以及计数器来计数数字采样器的输出，并向DCC提供控制以调整差分输出时钟的占空比。

4. 发明申请

WO2008140909A1 LC-TYPE VCO 审中-公开
公开(公告)号：WO2008140909A1
公开(公告)日：2008-11-20
申请号：PCT/US2008/061217
申请日：2008-04-23
申请人： INTEL CORPORATION , HYVONEN, Sami
发明人： HYVONEN, Sami
IPC分类号： H03B5/12 , H03L7/099
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1253 , H03B5/1265 , H03B5/1293 , H03B2200/0048 , H03B2200/005 , H03B2201/0208 , H03B2201/025 , H03J2200/10
摘要： Disclosed herein are embodiments of an LC-type VCO with multiple operational frequency bands having reasonably similar frequency vs. control signal slopes.
摘要翻译：这里公开了具有多个工作频带的具有合理相似的频率对控制信号斜率的LC型VCO的实施例。

5. 发明公开

EP4202592A1 DIGITAL VOLTAGE REGULATOR CURRENT SENSING AND REGULATION 审中-实审
公开(公告)号：EP4202592A1
公开(公告)日：2023-06-28
申请号：EP22208918.7
申请日：2022-11-22
申请人： INTEL Corporation
发明人： HODGSON, James Keith , PAILLET, Fabrice , MANDIC, Christopher J. , RENZEMA, Cary , RAMASUNDAR, Anand , HYVONEN, Sami , CHEN, Po-Cheng , RODRIGUEZ, Alex Santiago , RODRIGUEZ, Sergio Carlo , RAMAMOORTHY, Saravanan , SUVARNA, Ruthvin Jeevan
IPC分类号： G05F1/46 , G05F1/59
摘要： A reduced-size replica of power gate transistors may be used within a closed-loop voltage regulator to measure the average current delivered by the transistors in the non-replica power gate. The measured current is compared against a known reference current, and a feedback loop is used to modify the gate bias of the power gate and replica power gate transistors. An improved current sensing power gate replica solution may include measuring current from a small replica of the power gate and extrapolating the total current by digitally multiplying the replica current by the ratio of the size of the enabled power gates to the size of the replicas. The current through the replicas, which substantially matches the current in equivalent power gate devices, may be collected on an analog bus and conducted across a known resistor to generate a voltage that determines an estimated current of the power gate devices.

6. 发明公开

EP3072239A1 CLOCK CALIBRATION USING ASYNCHRONOUS DIGITAL SAMPLING 审中-公开
标题翻译： UHRENKALIBRIERUNG麻省理工大学毕业生ABTASTUNG
公开(公告)号：EP3072239A1
公开(公告)日：2016-09-28
申请号：EP13897939.8
申请日：2013-11-19
申请人： Intel Corporation
发明人： BALAMURUGAN, Ganesh , MANSURI, Mozhgan , HYVONEN, Sami , CASPER, Bryan K. , O'MAHONY, Frank
IPC分类号： H03L7/00 , H04L7/00
CPC分类号： H03L7/00 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03K5/1565 , H03L7/08 , H04B1/04 , H04L25/03
摘要： Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.
摘要翻译：描述了一种装置，包括：异步时钟发生器，用于产生异步时钟信号; 数字采样器，用于使用异步时钟信号对信号进行采样; 占空比校正器（DCC），用于接收差分输入时钟并产生差分输出时钟，其中数字采样器从差分输出时钟采样至少一个输出时钟; 以及计数器对数字采样器的输出进行计数，并向DCC提供控制以调整差分输出时钟的占空比。

7. 发明公开

EP3272084A1 HIGH SPEED RECEIVER WITH ONE-HOT DECISION FEEDBACK EQUALIZER 有权
标题翻译：具有单热判决反馈均衡器的高速接收器
公开(公告)号：EP3272084A1
公开(公告)日：2018-01-24
申请号：EP16765380.7
申请日：2016-02-10
申请人： Intel Corporation
发明人： VENKATRAM, Hariprasath , HYVONEN, Sami , MUSAH, Tawfiq , CASPER, Bryan K.
IPC分类号： H04L25/03 , H04L7/033
CPC分类号： H04L25/03057 , H04L7/0062 , H04L7/033 , H04L25/03878
摘要： Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

8. 发明公开

EP4203318A1 THERMOMETER ENCODING AND GANGING OF POWER GATES 审中-实审
公开(公告)号：EP4203318A1
公开(公告)日：2023-06-28
申请号：EP22206889.2
申请日：2022-11-11
申请人： INTEL Corporation
发明人： PAILLET, Fabrice , HYVONEN, Sami , MATTHEW, George , HODGSON, James , RAMASUNDAR, Anand , CHILKA, Sandeep , SOUNDARARAJAN, Bharadwaj , CARLO RODRIGUEZ, Sergio , CHEN, Po-Cheng , RENZEMA, Cary
IPC分类号： H03K19/00 , H03K19/003 , G05F1/10 , G05F1/46
摘要： A digitally selectable power gate with thermometer-encoded upper bits may provide solutions for problems digital power gate-based regulators. These solutions may include the use of a fully binary power gate, either in structure or by local decoding of binary control signal to an addressable row-based power gate. This provides improved performance over a row-based code rotation, which is intended to avoid instantaneous overheating of power gate devices but may not mitigate aging effects. Another solution includes ganging a primary DLVR and one or more secondaries. The primary DLVR may include a voltage sense and active controller, which may forward its PG code to secondary instances. Therm and current sensor rotation may be performed locally at the secondaries and a current monitor data may be rolled up from all ganged DLVRs.

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