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1. 发明申请

WO2019089045A1 TECHNIQUES FOR FORMING VIAS AND OTHER INTERCONNECTS FOR INTEGRATED CIRCUIT STRUCTURES 审中-公开
公开(公告)号：WO2019089045A1
公开(公告)日：2019-05-09
申请号：PCT/US2017/059980
申请日：2017-11-03
申请人： INTEL CORPORATION
发明人： MANIPATRUNI, Sasikanth , CHAWLA, Jasmeet S. , LIN, Chia-Ching , NIKONOV, Dmitri E. , YOUNG, Ian A. , BRISTOL, Robert L.
IPC分类号： H01L21/768 , H01L27/06
摘要： Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.

2. 发明申请

WO2018236354A1 METAL SPACER-BASED APPROACHES FOR CONDUCTIVE INTERCONNECT AND VIA FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2018236354A1
公开(公告)日：2018-12-27
申请号：PCT/US2017/038379
申请日：2017-06-20
申请人： INTEL CORPORATION , LIN, Kevin , SCHENKER, Richard E. , BRISTOL, Robert L. , KABIR, Nafees A. , VREELAND, Richard F.
发明人： LIN, Kevin , SCHENKER, Richard E. , BRISTOL, Robert L. , KABIR, Nafees A. , VREELAND, Richard F.
IPC分类号： H01L21/768
摘要： Metal spacer-based approaches for conductive interconnect and via fabrication is described. In an example, an integrated circuit structure includes a plurality of alternating first and second conductive lines along a same direction of a back end of line (BEOL) metallization layer in an inter-layer dielectric (ILD) structure above a substrate. Each of the plurality of alternating first and second conductive lines is recessed relative to an uppermost surface of the ILD structure. The ILD structure includes a plurality of first and second ILD lines alternating with the alternating first and second conductive lines. A first hardmask component is on and aligned with the first conductive lines. A second hardmask component is on an aligned with the second conductive lines. A conductive via is in an opening in the first hardmask component and on one of the first conductive lines.

3. 发明申请

WO2018111289A1 INTERCONNECTS PROVIDED BY SUBTRACTIVE METAL SPACER BASED DEPOSITION 审中-公开
公开(公告)号：WO2018111289A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/067069
申请日：2016-12-16
申请人： INTEL CORPORATION
发明人： BRISTOL, Robert L. , LIN, Kevin L. , GSTREIN, Florian
IPC分类号： H01L21/768 , H01L21/02 , H01L21/311
CPC分类号： H01L21/0337 , H01L21/76885 , H01L23/5283
摘要： Disclosed herein are methods for manufacturing a metallization stack including a plurality of electrically conductive interconnects by subtractive metal spacer based deposition, and related semiconductor devices. For example, in some embodiments, a method of forming a semiconductor device may include providing a pattern of sacrificial elements over an interconnect support layer, depositing an electrically conductive material on sidewalls of the sacrificial elements, and removing the sacrificial elements so that the remaining portions of the electrically conductive material form a pattern of electrically conductive elements which can serve as interconnects of a metallization stack of the semiconductor device.

4. 发明申请

WO2018063322A1 SPACER-BASED PATTERNING FOR TIGHT-PITCH AND LOW-VARIABILITY RANDOM ACCESS MEMORY (RAM) BIT CELLS AND THE RESULTING STRUCTURES 审中-公开
标题翻译：用于间距和低变量随机访问存储器（RAM）位单元的细胞间距图形和结果结构
公开(公告)号：WO2018063322A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054760
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： LIN, Kevin L. , ATANASOV, Sarah E. , O'BRIEN, Kevin P. , BRISTOL, Robert L.
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/00 , H01L45/085 , H01L45/1233 , H01L45/124 , H01L45/1266 , H01L45/141 , H01L45/147 , H01L45/1675
摘要： Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.
摘要翻译：描述了用于窄间距和低变异性随机存取存储器（RAM）位单元的基于间隔的图案化以及所产生的结构。在一个示例中，半导体结构包括具有顶层的衬底。非易失性随机存取存储器（RAM）位单元的阵列设置在衬底的顶层上。非易失性RAM位单元阵列包括沿着第一方向的非易失性RAM位单元的列和沿着与第一方向正交的第二方向的非易失性RAM位单元的行。沿着非易失性RAM位单元阵列的列之间的第一方向，衬底的顶层中有多个凹槽。

5. 发明申请

WO2018125023A1 METHODS FOR COMBINING MASK-BASED AND MASKLESS LITHOGRAPHY 审中-公开
公开(公告)号：WO2018125023A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068614
申请日：2016-12-26
申请人： INTEL CORPORATION
发明人： BRISTOL, Robert L. , LIN, Kevin L.
IPC分类号： G03F7/20 , H01L21/027
CPC分类号： G03F7/2051 , H01L21/0337 , H01L21/76807 , H01L21/76816
摘要： Disclosed herein are methods for manufacturing devices by combining mask-based and maskless lithography. For example, in some embodiments, a method of forming a semiconductor device may include performing a mask-based lithographic process on a substrate having one or more layers disposed thereon to form a set of mask-based features in a first layer of the one or more layers and performing a maskless lithographic process on the substrate to form a set of maskless features. Such a method allows to benefit from the advantages of both mask-based and maskless lithographic techniques. For example, mask-based lithography may be used to form most of the features while maskless lithography may be used to modify, delete, or add a relatively small number of features. In this manner, high throughput may be achieved by employing mask-based lithography while providing the flexibility in the features allowed by the use of maskless lithography.

6. 发明申请

WO2018031007A1 QUANTUM DOT ARRAY DEVICES 审中-公开
标题翻译：量子点阵器件
公开(公告)号：WO2018031007A1
公开(公告)日：2018-02-15
申请号：PCT/US2016/046236
申请日：2016-08-10
申请人： INTEL CORPORATION
发明人： CLARKE, James S. , BRISTOL, Robert L. , PILLARISETTY, Ravi , ROBERTS, Jeanette M. , GEORGE, Hubert C. , THOMAS, Nicole K.
IPC分类号： H01L29/66 , H01L29/12 , H01L29/80
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：包括量子阱层的量子阱堆; 设置在量子阱堆叠上方的多个栅极，其中至少两个栅极在量子阱堆叠上方的第一维度上间隔开，至少两个栅极在量子阱堆叠上方的第二维度间隔开，并且第一和第二尺寸是垂直的; 以及设置在所述量子阱堆叠上方的绝缘材料，其中所述绝缘材料在所述第一维度上间隔开的至少两个所述栅极之间延伸，并且所述绝缘材料在所述第二维度间隔开的至少两个栅极之间延伸。 / p>

7. 发明申请

WO2016209207A1 INTEGRATING MEMS STRUCTURES WITH INTERCONNECTS AND VIAS 审中-公开
标题翻译：用互连和VIAS集成MEMS结构
公开(公告)号：WO2016209207A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037024
申请日：2015-06-22
申请人： INTEL CORPORATION
发明人： LIN, Kevin Lai , PAWASHE, Chytra , KIM, Raseong , YOUNG, Ian A. , SINGH, Kanwal Jit , BRISTOL, Robert L.
IPC分类号： B81B7/02 , H01L21/8238
CPC分类号： B81B7/007 , B81B2203/0118 , B81B2207/015 , B81B2207/07 , B81B2207/094 , B81C1/00246 , B81C1/00301 , B81C2201/0109 , B81C2201/014 , B81C2203/0714 , B81C2203/0742 , B81C2203/0771
摘要： A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
摘要翻译：将导电层沉积在衬底上的牺牲层中的沟槽中。蚀刻停止层沉积在导电层上。去除牺牲层以形成间隙。在一个实施例中，光束在衬底上。横梁上有互连。蚀刻停止层在光束上。在光束和蚀刻停止层之间存在间隙。

8. 发明申请

WO2016105423A1 NOVEL METHOD FOR CREATING ALTERNATE HARDMASK CAP INTERCONNECT STRUCTURE WITH INCREASED OVERLAY MARGIN 审中-公开
标题翻译：用于创建具有增加的覆盖边界的替代HARDMASK CAP互连结构的新方法
公开(公告)号：WO2016105423A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072393
申请日：2014-12-24
申请人： INTEL CORPORATION
发明人： BRISTOL, Robert L. , CHANDHOK, Manish , CHAWLA, Jasmeet S. , GSTREIN, Florian , HAN, Eungnak , HOURANI, Rami , SCHENKER, Richard E. , YOUNKIN, Todd R. , LIN, Kevin
IPC分类号： H01L21/768 , H01L21/3205
CPC分类号： H01L23/528 , H01L21/76808 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76897 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/53295 , H01L2221/1026
摘要： Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first interconnect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.
摘要翻译：本发明的实施例包括互连结构和形成这种结构的方法。在一个实施例中，互连结构可以包括在ILD的顶表面上方的第一硬掩模层的层间电介质（ILD）。某些实施例包括ILD中的一个或多个第一互连线和位于每个第一互连线之上的第一介电帽。例如，第一电介质盖的表面可接触第一硬掩模层的顶表面。实施例还可以包括以与第一互连线交替模式布置的ILD中的一个或多个第二互连线。在一个实施例中，在每个第二互连线的顶表面上形成第二电介质盖。例如，第二电介质盖的表面接触第一硬掩模层的顶表面。

9. 发明申请

WO2015147843A1 PRECURSOR AND PROCESS DESIGN FOR PHOTO-ASSISTED METAL ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) 审中-公开
标题翻译：辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前驱物和工艺设计
公开(公告)号：WO2015147843A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/032073
申请日：2014-03-27
申请人： INTEL CORPORATION , BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
发明人： BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
IPC分类号： C23C16/455 , C23C16/52 , H01L21/285
CPC分类号： C23C16/45553 , C23C16/18 , C23C16/482 , H01L21/0337 , H01L21/28556 , H01L21/28562 , H01L21/76816 , H01L21/76879 , H01L21/76897 , H01L29/66795
摘要： Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.
摘要翻译：描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。

10. 发明申请

WO2015047345A1 FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIVE CHEMICAL REACTION INCLUDING LIMITING ENCROACHMENT OF THE LAYERS OVER ADJACENT REGIONS 审中-公开
标题翻译：通过选择性化学反应在小区域形成材料层，包括在相邻区域限制层的加强
公开(公告)号：WO2015047345A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062456
申请日：2013-09-27
申请人： INTEL CORPORATION , BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
发明人： BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
IPC分类号： H01L21/31
CPC分类号： H01L23/528 , H01L21/28562 , H01L21/288 , H01L21/3105 , H01L21/31058 , H01L21/311 , H01L21/32 , H01L21/32051 , H01L21/321 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.
摘要翻译：一个方面的方法包括通过分开地通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

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