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1. 发明申请

WO2019190453A1 SELECTIVE ETCHING AND CONTROLLED ATOMIC LAYER ETCHING OF TRANSITION METAL OXIDE FILMS FOR DEVICE FABRICATION 审中-公开
公开(公告)号：WO2019190453A1
公开(公告)日：2019-10-03
申请号：PCT/US2018/024294
申请日：2018-03-26
申请人： INTEL CORPORATION , BLACKWELL, James M. , CLENDENNING, Scott B. , TAN, Cen , KRYSAK, Marie
发明人： BLACKWELL, James M. , CLENDENNING, Scott B. , TAN, Cen , KRYSAK, Marie
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/768
摘要： Selective etching and controlled atomic layer etching of transition metal oxide films for device fabrication, and the resulting devices, are described. In an example, method of dry etching a film includes forming a transition metal oxide film having a latent pore-forming material therein. The method also includes removing a surface portion of the latent pore-forming material of the transition metal oxide film to form a porous region of the transition metal oxide film. The method also includes removing the porous region of the transition metal oxide film.

2. 发明申请

WO2019066825A1 PASSIVATION LAYER FOR GERMANIUM SUBSTRATE 审中-公开
公开(公告)号：WO2019066825A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053843
申请日：2017-09-27
申请人： INTEL CORPORATION , ROMERO, Patricio E. , CLENDENNING, Scott B. , GSTREIN, Florian , TAN, Cen
发明人： ROMERO, Patricio E. , CLENDENNING, Scott B. , GSTREIN, Florian , TAN, Cen
IPC分类号： H01L21/02 , H01L29/78
摘要： Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.

3. 发明申请

WO2018009158A1 CONFORMAL FILMS INCLUDING METAL GALLIUM CARBIDE AND METAL INDIUM CARBIDE FOR DEVICE APPLICATIONS AND THEIR FABRICATION 审中-公开
标题翻译：包含金属镓碳化物和金属铟碳化物的器件适用于器件应用及其制造
公开(公告)号：WO2018009158A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040894
申请日：2016-07-02
申请人： INTEL CORPORATION , CLENDENNING, Scott B. , KIM, Kyoung H. , ROMERO, Patricio E.
发明人： CLENDENNING, Scott B. , KIM, Kyoung H. , ROMERO, Patricio E.
IPC分类号： H01L21/28 , H01L21/02 , H01L29/78
摘要： An apparatus including an integrated circuit device structure including a metal layer including a composition of General Formula I: M-Al m -X 1 n -X 2 p -C q -O r , wherein M includes a metal selected from one or more of titanium, zirconium, hafnium, tantalum, niobium and vanadium, wherein C includes carbon, wherein X 1 includes gallium, wherein X 2 includes indium, wherein m, n, p, q and r represent an atomic percent of an element in the metal layer that can be 0 percent, with the proviso that n and p cannot each be 0 percent. A method including introducing a first precursor including a metal halide into a chamber including an integrated circuit structure, introducing a second precursor of at least one of an organogallium compound and organoindium compound into the chamber; and depositing a metal including the metal cation of the halide and at least one of gallium and indium.
摘要翻译：一种包括集成电路器件结构的设备，所述集成电路器件结构包括包含通式I的组成的金属层：M-Al m -X 1 ^{1 其中M包括一个或多个取代基，其中M包括一个或一个以上的取代基，选自钛，锆，铪，钽，铌和钒中的一种或多种的金属，其中C包括碳，其中X 1包括镓，其中X 2包括铟，其中m，n，p，q和r表示金属层中元素的原子百分比，其可以为0％，条件是n和p不能各为0％。包括将包含金属卤化物的第一前体引入包括集成电路结构的腔室中，将有机镓化合物和有机铟化合物中的至少一种的第二前体引入腔室中; 并沉积包括卤化物的金属阳离子和镓和铟中的至少一种的金属。}

4. 发明申请

WO2013162546A1 ENERGY STORAGE DEVICE, METHOD OF MANUFACTURING SAME, AND MOBILE ELECTRONIC DEVICE CONTAINING SAME 审中-公开
标题翻译：能量储存装置，其制造方法和含有其的移动电子装置
公开(公告)号：WO2013162546A1
公开(公告)日：2013-10-31
申请号：PCT/US2012/034972
申请日：2012-04-25
申请人： INTEL CORPORATION , GARDNER, Donald S. , PINT, Cary , CLENDENNING, Scott B.
发明人： GARDNER, Donald S. , PINT, Cary , CLENDENNING, Scott B.
IPC分类号： H01G4/005
CPC分类号： H01G11/02 , G06F1/1635 , H01G9/04 , H01G11/26 , H01G11/30 , H01G11/46 , H01G11/52 , H01G11/54 , H01G11/84 , H04M1/0262 , H04M2001/0204 , Y02E60/13 , Y10T29/49115
摘要： An energy storage device comprises a first porous semiconducting structure (510) comprising a first plurality of channels (511) that contain a first electrolyte (514) and a second porous semiconducting structure (520) comprising a second plurality of channels (521) that contain a second electrolyte (524). In one embodiment, the energy storage device further comprises a film (535) on at least one of the first and second porous semiconducting structures, the film comprising a material capable of exhibiting reversible electron transfer reactions. In another embodiment, at least one of the first and second electrolytes contains a plurality of metal ions. In another embodiment, the first and second electrolytes, taken together, comprise a redox system.
摘要翻译：能量存储装置包括第一多孔半导体结构（510），第一多孔半导体结构（510）包括含有第一电解质（514）的第一多个通道（511）和包含第二多个通道（521）的第二多孔半导体结构（520）第二电解质（524）。在一个实施例中，能量存储装置还包括在第一和第二多孔半导体结构中的至少一个上的膜（535），该膜包括能够显示可逆电子转移反应的材料。在另一个实施方案中，第一和第二电解质中的至少一个包含多个金属离子。在另一个实施方案中，第一和第二电解质一起组成氧化还原体系。

5. 发明申请

WO2018118086A1 GALLIUM-BASED CO-REACTANTS FOR FABRICATING METAL SILICIDE AND METAL GERMANIDE FILMS 审中-公开
公开(公告)号：WO2018118086A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068579
申请日：2016-12-23
申请人： INTEL CORPORATION , ROMERO, Patricio E. , CLENDENNING, Scott B. , TAN, Cen
发明人： ROMERO, Patricio E. , CLENDENNING, Scott B. , TAN, Cen
IPC分类号： H01L21/02 , C07F19/00
摘要： Gallium-based co-reactants for fabricating metal silicide and metal germanide films, and integrated circuit structures including such films, are described. In a first example, a discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a silicon-based moiety having a central silicon atom. The central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. In a second example, a discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a germanium-based moiety having a central germanium atom. The central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. In either case, a neutral Lewis basic ligand is bonded to the central gallium atom of the gallium-based moiety.

6. 发明申请

WO2016048336A1 SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的选择栅极间隔
公开(公告)号：WO2016048336A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057585
申请日：2014-09-26
申请人： INTEL CORPORATION , CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
发明人： CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/265 , H01L21/28247 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/66439 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
摘要翻译：讨论了与形成用于半导体器件和晶体管结构的选择性栅极间隔物以及使用这种技术形成的器件有关的技术。这样的技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同的表面化学性质的栅极，在栅极上形成选择性共形层，而不是在阻挡材料的一部分上，以及去除封闭材料的暴露部分。

7. 发明申请

WO2013147856A1 PROCESS AND MATERIAL FOR PREVENTING DELETERIOUS EXPANSION OF HIGH ASPECT RATIO COPPER FILLED THROUGH SILICON VIAS (TSVS) 审中-公开
标题翻译：用于防止通过硅酮（TSVS）填充的高比例铜的去除膨胀的方法和材料
公开(公告)号：WO2013147856A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031486
申请日：2012-03-30
申请人： INTEL CORPORATION , ZIMMERMAN, Paul A. , CLENDENNING, Scott B. , ROMERO, Patricio E. , FISCHER, Paul B. , EDGEWORTH, Robert
发明人： ZIMMERMAN, Paul A. , CLENDENNING, Scott B. , ROMERO, Patricio E. , FISCHER, Paul B. , EDGEWORTH, Robert
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/02205 , H01L21/0228 , H01L21/76831 , H01L21/76837 , H01L21/76841 , H01L21/76871 , H01L21/76879 , H01L23/481 , H01L23/60 , H01L23/642 , H01L25/0657 , H01L2224/16146 , H01L2225/06513 , H01L2225/06544
摘要： Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.
摘要翻译：公开了形成实现负热膨胀（NTE）材料如钨酸锆（ZrW2O8）或钨酸铪（HfW2O8）的穿硅通孔（TSV）的技术。在一些情况下，NTE材料设置在TSV的衬底和导电芯材之间，并且用于至少部分地抵消其间的热膨胀系数（CTE）失配，从而减少热诱导的应力和/或突出（泵送）导电芯材料。 NTE材料还可以防止导电芯材料的泄漏，电压击穿和/或扩散。此外，NTE材料可以降低高纵横比TSV中的径向应力。在一些情况下，本文公开的技术可以提高三维集成电路和/或其他三维封装中的TSV可靠性，增强三维集成和/或增强性能。根据本公开，可以使用本文描述的技术的其他实施例将是显而易见的。

8. 发明申请

WO2017052644A1 FABRICATION OF MULTI-CHANNEL NANOWIRE DEVICES WITH SELF-ALIGNED INTERNAL SPACERS AND SOI FINFETS USING SELECTIVE SILICON NITRIDE CAPPING 审中-公开
标题翻译：使用选择性硅氮化物封装的具有自对准的内部间隔器和SOI FinFET的多通道纳米器件的制造
公开(公告)号：WO2017052644A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052451
申请日：2015-09-25
申请人： INTEL CORPORATION , LE, Van, H. , CLENDENNING, Scott, B. , MITAN, Martin, M. , LIAO, Szuya, S.
发明人： LE, Van, H. , CLENDENNING, Scott, B. , MITAN, Martin, M. , LIAO, Szuya, S.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , B82Y10/00 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775
摘要： Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.
摘要翻译：公开了半导体器件表面的选择性氮化方法。例如，在翅片的顶部上形成硬掩模以产生SOI结构。硬掩模可以通过氮化翅片的顶部部分而形成。在其他实施例中，氮化硅生长在翅片的顶部以形成硬掩模。在另一个实例中，在栅极全环结构中在相邻的纳米线之间形成内部间隔物。内部间隔物可以通过在沟道区域和源区域和漏极区域之间氮化剩余的中间层材料来形成。

9. 发明申请

WO2015147843A1 PRECURSOR AND PROCESS DESIGN FOR PHOTO-ASSISTED METAL ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) 审中-公开
标题翻译：辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前驱物和工艺设计
公开(公告)号：WO2015147843A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/032073
申请日：2014-03-27
申请人： INTEL CORPORATION , BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
发明人： BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
IPC分类号： C23C16/455 , C23C16/52 , H01L21/285
CPC分类号： C23C16/45553 , C23C16/18 , C23C16/482 , H01L21/0337 , H01L21/28556 , H01L21/28562 , H01L21/76816 , H01L21/76879 , H01L21/76897 , H01L29/66795
摘要： Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.
摘要翻译：描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。

10. 发明申请

WO2015047345A1 FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIVE CHEMICAL REACTION INCLUDING LIMITING ENCROACHMENT OF THE LAYERS OVER ADJACENT REGIONS 审中-公开
标题翻译：通过选择性化学反应在小区域形成材料层，包括在相邻区域限制层的加强
公开(公告)号：WO2015047345A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062456
申请日：2013-09-27
申请人： INTEL CORPORATION , BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
发明人： BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
IPC分类号： H01L21/31
CPC分类号： H01L23/528 , H01L21/28562 , H01L21/288 , H01L21/3105 , H01L21/31058 , H01L21/311 , H01L21/32 , H01L21/32051 , H01L21/321 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.
摘要翻译：一个方面的方法包括通过分开地通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

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