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1. 发明申请

WO2015147843A1 PRECURSOR AND PROCESS DESIGN FOR PHOTO-ASSISTED METAL ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) 审中-公开
标题翻译：辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前驱物和工艺设计
公开(公告)号：WO2015147843A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/032073
申请日：2014-03-27
申请人： INTEL CORPORATION , BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
发明人： BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
IPC分类号： C23C16/455 , C23C16/52 , H01L21/285
CPC分类号： C23C16/45553 , C23C16/18 , C23C16/482 , H01L21/0337 , H01L21/28556 , H01L21/28562 , H01L21/76816 , H01L21/76879 , H01L21/76897 , H01L29/66795
摘要： Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.
摘要翻译：描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。

2. 发明申请

WO2015047345A1 FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIVE CHEMICAL REACTION INCLUDING LIMITING ENCROACHMENT OF THE LAYERS OVER ADJACENT REGIONS 审中-公开
标题翻译：通过选择性化学反应在小区域形成材料层，包括在相邻区域限制层的加强
公开(公告)号：WO2015047345A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062456
申请日：2013-09-27
申请人： INTEL CORPORATION , BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
发明人： BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
IPC分类号： H01L21/31
CPC分类号： H01L23/528 , H01L21/28562 , H01L21/288 , H01L21/3105 , H01L21/31058 , H01L21/311 , H01L21/32 , H01L21/32051 , H01L21/321 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.
摘要翻译：一个方面的方法包括通过分开地通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

3. 发明申请

WO2016048336A1 SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的选择栅极间隔
公开(公告)号：WO2016048336A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057585
申请日：2014-09-26
申请人： INTEL CORPORATION , CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
发明人： CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/265 , H01L21/28247 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/66439 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
摘要翻译：讨论了与形成用于半导体器件和晶体管结构的选择性栅极间隔物以及使用这种技术形成的器件有关的技术。这样的技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同的表面化学性质的栅极，在栅极上形成选择性共形层，而不是在阻挡材料的一部分上，以及去除封闭材料的暴露部分。

4. 发明申请

WO2018182637A1 BOTTOM-UP FILL USING BLOCKING LAYERS AND ADHESION PROMOTERS 审中-公开
公开(公告)号：WO2018182637A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025127
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： HOURANI, Rami , CLENDENNING, Scott B. , KLOSTER, Grant M. , MAESTRE CARO, Aranzazu , GSTREIN, Florian , CHOWDHURY, Akm Shaestagir , MAHDI, Tayseer
IPC分类号： H01L21/768
摘要： A device including a substrate formed of a material. The device includes a plurality of recessed features in a surface of the substrate, wherein the plurality of recessed features have an aspect ratio between 3:1-10:1, inclusive. The device includes a fill in the plurality of recessed features, wherein the fill is a second material that is different than the material of the substrate and wherein the fill covers sidewalls and bottom surfaces of the plurality of recessed features.

5. 发明申请

WO2017052610A1 TECHNIQUES FOR BOTTOM-UP FILLING OF THREE-DIMENSIONAL SEMICONDUCTOR DEVICE TOPOGRAPHIES 审中-公开
标题翻译：三维半导体器件拓扑图的底部填充技术
公开(公告)号：WO2017052610A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052304
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： KLOSTER, Grant M. , GSTREIN, Florian , CLENDENNING, Scott B. , HOURANI, Rami , FRASURE, Kent N.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L21/823821 , H01L21/823842 , H01L29/66795 , H01L29/785
摘要： Techniques are disclosed for bottom-up filling of semiconductor device topographies. In accordance with some embodiments, a seed layer may be formed over a bottom surface of a feature patterned in a dielectric layer. The seed layer may be, for example, a work function metal (WFM) layer or a barrier layer. In accordance with some embodiments, the fill metal may be, at least initially, selectively deposited over only the seed layer, and as deposition continues, the fill metal may grow to fill the feature from bottom to top, in some cases with no seam or void formed therein. Optional selective passivation of the sidewalls of the feature (or other layer therein) may inhibit fill metal deposition on those surfaces, facilitating selective deposition. In accordance with some embodiments, an etch and recess process that utilizes a sacrificial fill material may be used in forming the seed layer at the feature bottom.
摘要翻译：公开了用于半导体器件拓扑图的自底向上填充的技术。根据一些实施例，种子层可以形成在图案化在介电层中的特征的底表面上。种子层可以是例如功函数金属（WFM）层或阻挡层。根据一些实施例，填充金属可以至少最初选择性地沉积在种子层上，并且随着沉积的继续，填充金属可以生长以从底部到顶部填充该特征，在一些情况下，没有接缝或形成空隙。特征（或其中的其他层）的侧壁的任选的选择性钝化可以抑制这些表面上的填充金属沉积，促进选择性沉积。根据一些实施例，利用牺牲填充材料的蚀刻和凹陷工艺可用于在特征底部形成种子层。

6. 发明申请

WO2016204771A1 BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：用于半导体结构的金属特征的底部填充（BUF）
公开(公告)号：WO2016204771A1
公开(公告)日：2016-12-22
申请号：PCT/US2015/036519
申请日：2015-06-18
申请人： INTEL CORPORATION
发明人： CLENDENNING, Scott B. , MITAN, Martin M. , GLASSMAN, Timothy E. , GRIGGIO, Flavio , KLOSTER, Grant M. , FRASURE, Kent N. , GSTREIN, Florian , HOURANI, Rami
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76879 , C23C16/045 , H01L21/28 , H01L21/28556 , H01L21/28562 , H01L21/31144 , H01L21/76843 , H01L21/76861 , H01L21/76865 , H01L21/76876 , H01L29/66545 , H01L29/66795 , H01L2221/1063
摘要： Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.
摘要翻译：描述了用于形成半导体结构的金属特征的自底向上填充方法以及所得的结构。在一个示例中，半导体结构包括设置在层间电介质（ILD）层中的沟槽。沟槽有侧壁，底部和顶部。 U形金属种子层设置在沟槽的底部并且沿着沟槽的侧壁但基本上在沟槽的顶部下方。金属填充层设置在U形金属种子层上，并将沟槽填充到沟槽的顶部。金属填充层与U形金属种子层上方的沟槽的侧壁的部分直接接触ILD层的电介质材料。

7. 发明公开

EP3198652A1 SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的选择栅极间隔
公开(公告)号：EP3198652A1
公开(公告)日：2017-08-02
申请号：EP14902843.3
申请日：2014-09-26
申请人： INTEL Corporation
发明人： CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/265 , H01L21/28247 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/66439 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
摘要翻译：讨论了与用于形成用于半导体器件的选择性栅极隔离物和使用这种技术形成的晶体管结构和器件有关的技术。这种技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同表面化学性质的栅极，在栅极上而不是在阻挡材料的一部分上形成选择性共形层，并去除阻挡材料的暴露部分。

8. 发明公开

EP3311403A1 BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：底部填充（BUF）半导体结构的金属特征
公开(公告)号：EP3311403A1
公开(公告)日：2018-04-25
申请号：EP15895813.2
申请日：2015-06-18
申请人： Intel Corporation
发明人： CLENDENNING, Scott B. , MITAN, Martin M. , GLASSMAN, Timothy E. , GRIGGIO, Flavio , KLOSTER, Grant M. , FRASURE, Kent N. , GSTREIN, Florian , HOURANI, Rami
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76879 , C23C16/045 , H01L21/28 , H01L21/28556 , H01L21/28562 , H01L21/31144 , H01L21/76843 , H01L21/76861 , H01L21/76865 , H01L21/76876 , H01L29/66545 , H01L29/66795 , H01L2221/1063
摘要： Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.

9. 发明公开

EP3122918A1 PRECURSOR AND PROCESS DESIGN FOR PHOTO-ASSISTED METAL ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) 审中-公开
标题翻译： PRE和过程设计用于照片负载金属原子层沉积（ALD）和化学气相沉积（CVD）
公开(公告)号：EP3122918A1
公开(公告)日：2017-02-01
申请号：EP14887657.6
申请日：2014-03-27
申请人： Intel Corporation
发明人： BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
IPC分类号： C23C16/455 , C23C16/52 , H01L21/285
CPC分类号： C23C16/45553 , C23C16/18 , C23C16/482 , H01L21/0337 , H01L21/28556 , H01L21/28562 , H01L21/76816 , H01L21/76879 , H01L21/76897 , H01L29/66795
摘要： Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.
摘要翻译：描述前体和工艺设计光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）。在一个实例中，制造薄金属的方法薄膜涉及引入邻近的前体分子在表面上或上方的衬底，每一个都具有被配体包围的一个或多个金属中心的前体分子。因此，该方法包括通过离解从使用光辅助过程中的前体分子的配位体沉积在表面上的金属层。

10. 发明公开

EP3050084A1 FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIVE CHEMICAL REACTION INCLUDING LIMITING ENCROACHMENT OF THE LAYERS OVER ADJACENT REGIONS 审中-公开
标题翻译：物料对小区域通过选择性化学反应的层与层的在蔓延邻近地区CONTROLS生产
公开(公告)号：EP3050084A1
公开(公告)日：2016-08-03
申请号：EP13894765.0
申请日：2013-09-27
申请人： Intel Corporation
发明人： BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
IPC分类号： H01L21/31
CPC分类号： H01L23/528 , H01L21/28562 , H01L21/288 , H01L21/3105 , H01L21/31058 , H01L21/311 , H01L21/32 , H01L21/32051 , H01L21/321 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

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