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1. 发明申请

WO2019190463A1 MULTIFUNCTIONAL MOLECULES FOR SELECTIVE POLYMER FORMATION ON CONDUCTIVE SURFACES AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2019190463A1
公开(公告)日：2019-10-03
申请号：PCT/US2018/024364
申请日：2018-03-26
申请人： INTEL CORPORATION , HAN, Eungnak , MAHDI, Tayseer , HOURANI, Rami , SINGH, Gurpreet , GSTREIN, Florian
发明人： HAN, Eungnak , MAHDI, Tayseer , HOURANI, Rami , SINGH, Gurpreet , GSTREIN, Florian
IPC分类号： H01L21/768 , H01L21/02 , H01L21/027 , G03F7/20
摘要： Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

2. 发明申请

WO2018118090A1 CONDUCTIVE CAP-BASED APPROACHES FOR CONDUCTIVE VIA FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2018118090A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068583
申请日：2016-12-23
申请人： INTEL CORPORATION
发明人： GSTREIN, Florian , HAN, Eungnak , HOURANI, Rami , BRAIN, Ruth A. , NYHUS, Paul A. , CHANDHOK, Manish , WALLACE, Charles H. , TSANG, Chi-Hwa
IPC分类号： H01L21/768
摘要： Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

3. 发明申请

WO2016105423A1 NOVEL METHOD FOR CREATING ALTERNATE HARDMASK CAP INTERCONNECT STRUCTURE WITH INCREASED OVERLAY MARGIN 审中-公开
标题翻译：用于创建具有增加的覆盖边界的替代HARDMASK CAP互连结构的新方法
公开(公告)号：WO2016105423A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072393
申请日：2014-12-24
申请人： INTEL CORPORATION
发明人： BRISTOL, Robert L. , CHANDHOK, Manish , CHAWLA, Jasmeet S. , GSTREIN, Florian , HAN, Eungnak , HOURANI, Rami , SCHENKER, Richard E. , YOUNKIN, Todd R. , LIN, Kevin
IPC分类号： H01L21/768 , H01L21/3205
CPC分类号： H01L23/528 , H01L21/76808 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76897 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/53295 , H01L2221/1026
摘要： Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first interconnect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.
摘要翻译：本发明的实施例包括互连结构和形成这种结构的方法。在一个实施例中，互连结构可以包括在ILD的顶表面上方的第一硬掩模层的层间电介质（ILD）。某些实施例包括ILD中的一个或多个第一互连线和位于每个第一互连线之上的第一介电帽。例如，第一电介质盖的表面可接触第一硬掩模层的顶表面。实施例还可以包括以与第一互连线交替模式布置的ILD中的一个或多个第二互连线。在一个实施例中，在每个第二互连线的顶表面上形成第二电介质盖。例如，第二电介质盖的表面接触第一硬掩模层的顶表面。

4. 发明申请

WO2015047345A1 FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIVE CHEMICAL REACTION INCLUDING LIMITING ENCROACHMENT OF THE LAYERS OVER ADJACENT REGIONS 审中-公开
标题翻译：通过选择性化学反应在小区域形成材料层，包括在相邻区域限制层的加强
公开(公告)号：WO2015047345A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062456
申请日：2013-09-27
申请人： INTEL CORPORATION , BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
发明人： BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
IPC分类号： H01L21/31
CPC分类号： H01L23/528 , H01L21/28562 , H01L21/288 , H01L21/3105 , H01L21/31058 , H01L21/311 , H01L21/32 , H01L21/32051 , H01L21/321 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.
摘要翻译：一个方面的方法包括通过分开地通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

5. 发明申请

WO2022066336A1 CONTACT OVER ACTIVE GATE STRUCTURES USING DIRECTED SELF-ASSEMBLY FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION 审中-公开
公开(公告)号：WO2022066336A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/047265
申请日：2021-08-24
申请人： INTEL CORPORATION
发明人： NYHUS, Paul A. , WALLACE, Charles H. , CHANDHOK, Manish , HARAN, Mohit K. , SINGH, Gurpreet , HAN, Eungnak , GSTREIN, Florian , SCHENKER, Richard E. , SHYKIND, David , ALOYSIUS, Jinnie , PURSEL, Sean
IPC分类号： H01L21/8234 , H01L21/02 , H01L21/768 , G06F1/16
摘要： Contact over active gate (COAG) structures are described. An integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.

6. 发明申请

WO2018063318A1 PHOTOBUCKET FLOOR COLORS WITH SELECTIVE GRAFTING 审中-公开
标题翻译：采用选择性接枝的照相馆地板颜色
公开(公告)号：WO2018063318A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054742
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： BRISTOL, Robert L. , LIN, Kevin L. , BLACKWELL, James M. , HOURANI, Rami , HAN, Eungnak
IPC分类号： H01L21/768
摘要： Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.
摘要翻译：描述了基于具有用于半导体结构制造的选择性接枝的光桶底颜色以及所得到的结构的方法。例如，在衬底上方形成的ILD层上方形成光栅结构，该光栅结构包括由交替的第一沟槽和第二沟槽分开的多个电介质间隔体，在第一沟槽中接枝抗蚀剂 - 阻挡层但在第二沟槽中接枝抗蚀剂 - 在第一沟槽和第二沟槽中形成光致抗蚀剂，将选定的第二沟槽中的光致抗蚀剂曝光和去除到光刻曝光以限定一组通孔位置，将该组通孔位置蚀刻到ILD层中，以及在ILD层中形成多个金属线，其中多个金属线中的选定线包括对应于该组通孔位置的下面的导电通孔。

7. 发明申请

WO2018004699A1 LINED PHOTOBUCKET STRUCTURE FOR BACK END OF LINE (BEOL) INTERCONNECT FORMATION 审中-公开
标题翻译：线状（光束）互连结构后端内置光匣结构
公开(公告)号：WO2018004699A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040876
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： BLACKWELL, James M. , BRISTOL, Robert L. , KRYSAK, Marie , GSTREIN, Florian , HAN, Eungnak , LIN, Kevin L. , HOURANI, Rami , HARLSON, Shane M.
IPC分类号： H01L21/768 , H01L21/027 , G03F7/20
CPC分类号： G03F7/0035 , G03F7/0002 , G03F7/40 , H01L21/027 , H01L21/0274 , H01L21/768 , H01L21/76802
摘要： Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
摘要翻译：描述了衬里光刻胶结构以便于制造后端线路（BEOL）互连。在一个实施例中，硬掩模具有形成于其中的凹槽，其中衬垫结构各自设置在相应凹槽的侧壁上。包括光致抗蚀剂材料的光阑也不同地设置在凹陷中。衬垫结构不同地用作边缘缓冲器以减轻光致抗蚀剂材料暴露于光子或电子束中的未对准的可能影响。在另一个实施方案中，凹槽中设置有衬底结构和光桶，它们都是通过光刻胶基嵌段共聚物的自组装形成的。

8. 发明申请

WO2014209327A1 NON-LITHOGRAPHICALLY PATTERNED DIRECTED SELF ASSEMBLY ALIGNMENT PROMOTION LAYERS 审中-公开
标题翻译：非平面图形自动对齐自组织对齐促销层
公开(公告)号：WO2014209327A1
公开(公告)日：2014-12-31
申请号：PCT/US2013/048307
申请日：2013-06-27
申请人： INTEL CORPORATION , BRISTOL, Robert L. , HOURANI, Rami , HAN, Eungnak , BLACKWELL, James M.
发明人： BRISTOL, Robert L. , HOURANI, Rami , HAN, Eungnak , BLACKWELL, James M.
IPC分类号： H01L21/027 , H01L21/28
CPC分类号： H01L21/76897 , B81C1/00031 , B81C2201/0149 , H01L21/02118 , H01L21/0271 , H01L21/31051 , H01L21/31127 , H01L21/76822 , H01L21/76834 , H01L23/528 , H01L23/5328 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.
摘要翻译：一个方面的方法包括在具有第一图案化区域和第二图案化区域的基板的表面上形成定向自组装对准促进层。选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

9. 发明申请

WO2021247195A1 DIRECTED SELF-ASSEMBLY STRUCTURES AND TECHNIQUES 审中-公开
公开(公告)号：WO2021247195A1
公开(公告)日：2021-12-09
申请号：PCT/US2021/031203
申请日：2021-05-07
申请人： INTEL CORPORATION
发明人： BLACKWELL, James, Munro , BRISTOL, Robert, L. , CHEN, Xuanxuan , DOYLE, Lauren, Elizabeth , GSTREIN, Florian , HAN, Eungnak , HOLYBEE, Brandon, Jay , KRYSAK, Marie , MAHDI, Tayseer , SCHENKER, Richard, E. , SINGH, Gurpreet , WALKER, Emily, Susan
IPC分类号： H01L23/485 , H01L23/535 , H01L23/538 , G03F7/0002
摘要： Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

10. 发明申请

WO2018125089A1 GRATING LAYER WITH VARIABLE PITCH FORMED USING DIRECTED SELF-ASSEMBLY OF MULTIBLOCK COPOLYMERS 审中-公开
公开(公告)号：WO2018125089A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068931
申请日：2016-12-28
申请人： INTEL CORPORATION
发明人： SINGH, Gurpreet , HAN, Eungnak , GSTREIN, Florian
IPC分类号： H01L21/768
CPC分类号： H01L21/76829 , H01L21/76834 , H01L21/76897
摘要： Disclosed herein are integrated circuits incorporating grating layers with variable pitch, and methods of producing the same. In one implementation, an integrated circuit comprises a substrate and a grating layer formed above the substrate. The grating layer comprising metal regions separated from each other by dielectric spacers, having variable metal-to-metal pitch throughout the grating layer. The integrated circuit further comprises a hard mask layer formed above the grating layer, and a via formed through the hard mask layer to electrically couple a first metal region of the grating layer to an upper interconnect structure.

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