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1. 发明申请

WO2019190686A1 TECHNOLOGIES FOR COOPERATIVE LINK EQUALIZATION WITHOUT DISRUPTION TO LINK TRAFFIC 审中-公开
公开(公告)号：WO2019190686A1
公开(公告)日：2019-10-03
申请号：PCT/US2019/019962
申请日：2019-02-28
申请人： INTEL CORPORATION
发明人： SHAH, Nishantkumar , LILLIE, Kevan A. , RAN, Adee Ofir , LEVIN, Itamar , LUSTED, Kent C.
IPC分类号： H04L25/03 , H04L29/08 , H04L12/26
摘要： Technologies for cooperative link equalization include a network device with a network interface controller (NIC). The NIC is to monitor variation in a property of a link channel that connects the network device with a target network device. The NIC detects, based on the channel variation, an event that triggers a condition to change an equalization setting of the link channel. In response to the detection, the NIC communicates, via an in-band equalization control channel, changes to the equalization setting of the link channel to the target network device.

2. 发明申请

WO2018049164A1 TECHNIQUES FOR LINK PARTNER ERROR REPORTING 审中-公开
标题翻译：链接伙伴错误报告的技巧
公开(公告)号：WO2018049164A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/050684
申请日：2017-09-08
申请人： INTEL CORPORATION
发明人： RAN, Adee O. , BENHAMOU, Assaf , LANDAU, Yoni , MEZER, Amir , LEVIN, Itamar , MEISLER, Alon
IPC分类号： H04L1/00 , H03M13/15
CPC分类号： H03M13/015 , H03M13/09 , H03M13/13 , H03M13/15 , H03M13/1515 , H03M13/353 , H04L1/203
摘要： Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.
摘要翻译：描述了用于提供链接伙伴健康报告的计算设备和技术。在一个实施例中，例如，装置可以包括至少一个存储器和逻辑，所述逻辑的至少一部分包括在耦合到所述至少一个存储器的硬件中，所述逻辑确定多个错误计数器，每个与多个错误相关联的多个错误计数器确定与数据块相关联的多个数据单元中的每个数据单元的错误数量，将与每个数据单元的错误数量相对应的多个错误计数器中的每一个递增将所述数据块的多个错误计数提供给链接伙伴，所述多个错误计数对应于在所述数据块的所述多个错误计数器中的每一个中累积的错误的数量，并且将所述多个错误计数器多个错误计数器。描述并要求保护其他实施例。

3. 发明申请

WO2016099725A1 DELAY RESILIENT DECISION FEEDBACK EQUALIZER 审中-公开
标题翻译：延迟回馈决策反馈平均
公开(公告)号：WO2016099725A1
公开(公告)日：2016-06-23
申请号：PCT/US2015/060440
申请日：2015-11-12
申请人： INTEL CORPORATION
发明人： LAUFER, Amir , LEVIN, Itamar
IPC分类号： H04L25/03 , H04L25/08
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03579
摘要： Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.
摘要翻译：描述了一种装置，其包括具有第一DFE抽头路径和非第一DFE抽头路径的判决反馈均衡器（DFE），其中DFE在非第一DFE抽头路径的信号路径中包括可变延迟电路。在一些实施例中，提供一种装置，包括：一个夏天; 从夏天接收输入的切片机; 第一反馈回路，以消除第一后视标，所述第一反馈回路通过将所述限幅器耦合到所述夏季而形成回路; 以及用于消除第二后置光标的第二反馈回路，所述第二反馈回路通过将所述第一反馈回路的输入耦合到所述加法器来形成回路，其中所述第二反馈回路在其输入处具有可编程延迟。

4. 发明申请

WO2022132254A1 ANALOG EQUALIZATION WITH PEAKING AND SLOPE CONTROL 审中-公开
公开(公告)号：WO2022132254A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/049897
申请日：2021-09-10
申请人： INTEL CORPORATION
发明人： LEVIN, Itamar , GRAFI, Tali Warshavsky , CUSMAI, Marco , BALANKUTTY, Ajay , SHIVA KIRAN, Fnu , COHEN, Ariel
IPC分类号： H04L25/03
摘要： An apparatus comprising at least one medium to transport a signal and an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises independently tunable parameters including a peak frequency gain and a mid-range frequency response slope. The independently tunable parameters of the analog equalization circuit include a low frequency de-emphasis amount.

5. 发明申请

WO2017053770A1 ACTIVE LINK DURING LAN INTERFACE RESET 审中-公开
标题翻译：局域网接口复位时的主动链路
公开(公告)号：WO2017053770A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/053398
申请日：2016-09-23
申请人： INTEL CORPORATION
发明人： TAMIR, Eliezer , FRIEDMAN, Ben-Zion , LEVIN, Itamar
IPC分类号： H04L12/28 , H04L29/10 , H04L12/931
CPC分类号： H04L69/322 , H04L41/0816 , H04L47/266 , H04L47/30 , H04L49/9068 , H04L67/145 , H04L69/24
摘要： Methods and apparatus for supporting active link status during LAN interface reset and reconfigurations. Under one method, in response to a link reset event, transmit (TX) queues for a NIC are suspended and the TX pipe is drained. A PHY "Pause" packet is sent to a link partner for the NIC, and the NIC waits for an Ack to the Pause packet and for its receive (RX) pipe to drain. A link pause status is reported to software (e.g., an operating system or NIC device driver), which informs the software not to take the link down. The (re)configuration update process is performed, and information indicating the pause has ended is reported to the link partner and the software.
摘要翻译：在LAN接口复位和重新配置期间支持主动链路状态的方法和装置。在一种方法下，响应于链路重置事件，NIC的传输（TX）队列被暂停并且TX管道被排出。 PHY“暂停”数据包被发送到NIC的链路伙伴，并且NIC等待Ack到暂停数据包，并且其接收（RX）管道泄漏。向软件（例如，操作系统或NIC设备驱动程序）报告链接暂停状态，软件通知软件不将连接断开。执行（重新）配置更新处理，并且指示暂停的信息被报告给链路伙伴和软件。

6. 发明申请

WO2015148062A1 CENTRALIZED SECURITY FOR A COMPUTING DEVICE 审中-公开
标题翻译：用于计算设备的集中安全
公开(公告)号：WO2015148062A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/018340
申请日：2015-03-02
申请人： INTEL CORPORATION
发明人： AVNI, Noam , LEVIN, Itamar
IPC分类号： G06F21/88 , G06F21/31
CPC分类号： G06F21/81 , G06F21/31 , G06F21/32 , G06F21/88 , G06F2221/2111
摘要： A security procedure may be triggered in response to a detected activation event to release a lock securing a computing device, initiate the security procedure responsive to the activation event, enable a secure computing mode on the computing device, request authentication data, verify the authentication data and send a command to release the lock responsive to verification of the authentication data.
摘要翻译：可以响应于检测到的激活事件来触发安全过程以释放保护计算设备的锁定，响应于激活事件发起安全过程，使得计算设备上的安全计算模式能够请求认证数据，验证认证数据并响应于认证数据的验证发送命令释放锁。

7. 发明公开

EP3353959A1 ACTIVE LINK DURING LAN INTERFACE RESET 有权
公开(公告)号：EP3353959A1
公开(公告)日：2018-08-01
申请号：EP16849732.9
申请日：2016-09-23
申请人： INTEL Corporation
发明人： TAMIR, Eliezer , FRIEDMAN, Ben-Zion , LEVIN, Itamar
IPC分类号： H04L12/28 , H04L29/10 , H04L12/931
CPC分类号： H04L67/145 , H04L12/28 , H04L41/0816 , H04L47/24 , H04L47/266 , H04L47/30 , H04L49/9068 , H04L67/025 , H04L69/24 , H04L69/322 , H04L69/323 , H04L69/324
摘要： Methods and apparatus for supporting active link status during LAN interface reset and reconfigurations. Under one aspect, during normal operations traffic is transmitted over an Ethernet link coupling a first link partner to a second link partner. In response to a network interface re-configuration event, transmission of traffic over the Ethernet link is paused while keeping the Physical layer (PHY) of the Ethernet link active. The configuration of the first link partner is updated while the transmission of traffic is paused and the PHY of the Ethernet link is active. Upon completion of the configuration update, the link partners resume transmission of traffic over the Ethernet link. Additional schemes are provided that support re-configuration of network interfaces that support link and per priority flow control. According to another aspect, separate power domains are used for the PHY and the MAC circuitry, enabling the MAC circuitry to be reset via a power cycle while maintaining power to the PHY circuitry.

8. 发明公开

EP4264896A1 ANALOG EQUALIZATION WITH PEAKING AND SLOPE CONTROL 审中-实审
公开(公告)号：EP4264896A1
公开(公告)日：2023-10-25
申请号：EP21907371.5
申请日：2021-09-10
申请人： Intel Corporation
发明人： LEVIN, Itamar , GRAFI, Tali Warshavsky , CUSMAI, Marco , BALANKUTTY, Ajay , SHIVA KIRAN, Fnu , COHEN, Ariel
IPC分类号： H04L25/03

9. 发明公开

EP4199440A1 SCALABLE RECEIVER ARCHITECTURE FOR SILICON PHOTONIC LINKS 审中-实审
公开(公告)号：EP4199440A1
公开(公告)日：2023-06-21
申请号：EP22206895.9
申请日：2022-11-11
申请人： INTEL Corporation
发明人： RAN, Adee Ofir , LEVIN, Itamar
IPC分类号： H04L25/03 , H04L25/497
摘要： Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.

10. 发明公开

EP3235203A1 DELAY RESILIENT DECISION FEEDBACK EQUALIZER 审中-公开
标题翻译：延迟韧性决策反馈均衡器
公开(公告)号：EP3235203A1
公开(公告)日：2017-10-25
申请号：EP15870558.2
申请日：2015-11-12
申请人： Intel Corporation
发明人： LAUFER, Amir , LEVIN, Itamar
IPC分类号： H04L25/03 , H04L25/08
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03579
摘要： Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.
摘要翻译：描述了包括具有第一DFE抽头路径和非第一DFE抽头路径的判定反馈均衡器（DFE）的设备，其中DFE在非第一DFE抽头路径的信号路径中包括可变延迟电路。在一些实施例中，提供了一种装置，其包括：夏天; 一台切片机接受来自夏季的输入; 用于取消第一后标志的第一反馈回路，所述第一反馈回路通过将所述限幅器耦合到所述夏季而形成回路; 以及用于取消第二后标的第二反馈回路，所述第二反馈回路通过将所述第一反馈回路的输入耦合到所述加法器而形成回路，其中所述第二反馈回路在其输入处具有可编程延迟。

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