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1. 发明申请

WO2012087561A3 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 审中-公开
标题翻译：硬件和软件系统自动将程序分解为多个并行线程的系统，装置和方法
公开(公告)号：WO2012087561A3
公开(公告)日：2012-08-16
申请号：PCT/US2011063466
申请日：2011-12-06
申请人： INTEL CORP , SAGER DAVID J , SASANKA RUCHIRA , GABOR RON , RAIKIN SHLOMO , NUZMAN JOSEPH , PELED LEEOR , DOMER JASON A , KIM HO-SEOP , WU YOUFENG , YAMADA KOICHI , NGAI TIN-FOOK , CHEN HOWARD H , BOBBA JAYARAM , COOK JEFFREY J , SHAIKH OSMAR M , SRINIVAS SURESH
发明人： SAGER DAVID J , SASANKA RUCHIRA , GABOR RON , RAIKIN SHLOMO , NUZMAN JOSEPH , PELED LEEOR , DOMER JASON A , KIM HO-SEOP , WU YOUFENG , YAMADA KOICHI , NGAI TIN-FOOK , CHEN HOWARD H , BOBBA JAYARAM , COOK JEFFREY J , SHAIKH OSMAR M , SRINIVAS SURESH
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解成多个并行线程的硬件和软件系统的系统，设备和方法。在一些实施例中，系统和设备执行原始代码分解和/或生成的线程执行的方法。

2. 发明申请

WO0239269A3 APPARATUS AND METHOD TO RESCHEDULE INSTRUCTIONS 审中-公开
标题翻译：装置说明书和方法
公开(公告)号：WO0239269A3
公开(公告)日：2003-01-23
申请号：PCT/US0150735
申请日：2001-10-18
申请人： INTEL CORP , CARMEAN DOUGLAS M , BOGGS DARRELL D , SAGER DAVID J , MCKEEN FRANCIS X , HAMMARLUND PER , SINGHAL RONAK
发明人： CARMEAN DOUGLAS M , BOGGS DARRELL D , SAGER DAVID J , MCKEEN FRANCIS X , HAMMARLUND PER , SINGHAL RONAK
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprise a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled tot he execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重新安排的重播队列在处理器中重新播放依赖循环。处理器包括用于接收多个指令的重播队列，以及执行多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。检查器与执行单元相连以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

3. 发明申请

WO0242902A2 RESCHEDULING MULTIPLE MICRO-OPERATIONS IN A PROCESSOR USING A REPLAY QUEUE 审中-公开
标题翻译：使用REPLAY QUEUE对处理器中的多个微操作进行排序
公开(公告)号：WO0242902A2
公开(公告)日：2002-05-30
申请号：PCT/US0151023
申请日：2001-10-18
申请人： INTEL CORP , CARMEAN DOUGLAS M , BOGGS DARRELL D , SAGER DAVID J , MCKEEN FRANCIS X , HAMMARLUND PER , SINGHAL RONAK
发明人： CARMEAN DOUGLAS M , BOGGS DARRELL D , SAGER DAVID J , MCKEEN FRANCIS X , HAMMARLUND PER , SINGHAL RONAK
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is couple to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重放队列在处理器中重新安排多个微操作。处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地安排执行指令并将每个指令分派到执行单元。检查器耦合到执行单元，以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

4. 发明申请

WO0017757A3 REDUNDANT FORM ADDRESS DECODER FOR MEMORY SYSTEM 审中-公开
标题翻译：用于存储系统的冗余形式地址解码器
公开(公告)号：WO0017757A3
公开(公告)日：2000-07-13
申请号：PCT/US9927873
申请日：1999-08-27
申请人： INTEL CORP
发明人： SAGER DAVID J
IPC分类号： G11C8/00 , G06F7/52
CPC分类号： G11C8/00
摘要： The present invention provides a memory system (200) that retrieves data based upon redundant form address data. The memory system (200) includes a memory (220) having a plurality of memory lines (222) and an address decoder (210) that enables one of the memory lines (222) in response to a redundant form address signal. A redundant form decoder (230) decodes redundant form data into a differential pair of decoded address lines for each bit position of a memory address. One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line by memory line basis, using the address of the memory lines themselves. The redundant form address decoder (230) avoids a completion add that would otherwise be required, yielding very fast access to memory.
摘要翻译：本发明提供了一种基于冗余形式地址数据检索数据的存储器系统（200）。存储器系统（200）包括具有多个存储器线（222）和地址解码器（210）的存储器（220），其能够响应于冗余形式地址信号使存储器线路（222）中的一个能够被存储。冗余形式解码器（230）将冗余形式数据解码为存储器地址的每个位位置的解码地址线的差分对。两个差分对之一承载正确的地址数据。要使用的一条地址线使用存储器线本身的地址在存储器线的基础上由存储器线确定。冗余形式地址解码器（230）避免了否则将需要的完成添加，从而非常快速地访问存储器。

5. 发明公开

EP1129409A4 REDUNDANT FORM ADDRESS DECODER FOR MEMORY SYSTEM 有权
标题翻译：解码器，用于存储系统的冗余详情
公开(公告)号：EP1129409A4
公开(公告)日：2003-07-30
申请号：EP99965886
申请日：1999-08-27
申请人： INTEL CORP
发明人： SAGER DAVID J
IPC分类号： G11C8/00 , G11C8/08 , G11C8/10
CPC分类号： G11C8/00
摘要： The present invention provides a memory system (200) that retrieves data based upon redundant form address data. The memory system (200) includes a memory (220) having a plurality of memory lines (222) and an address decoder (210) that enables one of the memory lines (222) in response to a redundant form address signal. A redundant form decoder (230) decodes redundant form data into a differential pair of decoded address lines for each bit position of a memory address. One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line by memory line basis, using the address of the memory lines themselves. The redundant form address decoder (230) avoids a completion add that would otherwise be required, yielding very fast access to memory.

6. 发明公开

EP1151383A4 CONTENT ADDRESSABLE MEMORY ADDRESSABLE BY REDUNDANT FORM INPUT DATA 有权
标题翻译： BY重复输入数据内容可寻址存储器
公开(公告)号：EP1151383A4
公开(公告)日：2004-06-16
申请号：EP99937784
申请日：1999-08-03
申请人： INTEL CORP
发明人： SAGER DAVID J
IPC分类号： G06F7/38 , G11C15/00 , G11C15/04 , G06F12/02
CPC分类号： G11C15/04 , G06F7/38 , G11C15/00
摘要： A content addressable memory (200) compares the value of redundant form input data to non-redundant form values stored in registers (220s) of the memory. The memory decodes the redundant form input data in a data decoder (210). Thereafter, the CAM performs match detection on the decoded data. The decoding and match detection are performed more quickly than traditional adders and even more quickly than complete redundant form adders.

7. 发明公开

EP1198747A4 TRACE BASED INSTRUCTION CACHING 审中-公开
标题翻译： COMMAND缓存存储基于流量数据
公开(公告)号：EP1198747A4
公开(公告)日：2005-03-16
申请号：EP99902317
申请日：1999-01-15
申请人： INTEL CORP
发明人： KRICK ROBERT F , HINTON GLENN J , UPTON MICHAEL D , SAGER DAVID J , LEE CHAN W
IPC分类号： G06F9/32 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3836 , G06F12/0875
摘要： A cache memory (10) is constituted with a data array (14) and control logic (26). The data array (14) includes a number of data lines, and the control logic (26) operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more basic blocks of instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

8. 发明专利

GB2512727B Tracking control flow of instructions 未知
公开(公告)号：GB2512727B
公开(公告)日：2015-10-21
申请号：GB201402938
申请日：2014-02-19
申请人： INTEL CORP
发明人： BOBBA JAYARAM , SASANKA RUCHIRA , COOK JEFFREY J , DAS ABHINAV , KRISHNASWAMY ARVIND , SAGER DAVID J , AGRON JASON M
IPC分类号： G06F9/30 , G06F1/32 , G06F9/455 , G06F11/34 , G06F11/36

9. 发明专利

GB2410104B Method and apparatus for assigning thread priority in a multi-threaded processor 未知
公开(公告)号：GB2410104B
公开(公告)日：2005-11-02
申请号：GB0506377
申请日：2002-04-18
申请人： INTEL CORP
发明人： BOGGS DARRELL D , SAGER DAVID J , UPTON MICHAEL D , ALLEN JAMES , BURNS DAVID
IPC分类号： G06F9/38 , G06F9/48 , G06F9/46

10. 发明专利

GB2368165A8 Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor 未知
公开(公告)号：GB2368165A8
公开(公告)日：2004-07-07
申请号：GB0200078
申请日：2000-06-26
申请人： INTEL CORP
发明人： SAGER DAVID J
IPC分类号： G06F9/48 , C06F9/46

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