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    • 2. 发明申请
    • PROTECTING THE INTEGRITY OF BINARY TRANSLATED CODE
    • 保护二进制翻译代码的完整性
    • WO2013101125A1
    • 2013-07-04
    • PCT/US2011/067974
    • 2011-12-29
    • INTEL CORPORATIONRAIKIN, ShlomoRAPPOPORT, LihuNUZMAN, Joseph
    • RAIKIN, ShlomoRAPPOPORT, LihuNUZMAN, Joseph
    • G06F9/30G06F9/305G06F15/80G06F13/38
    • G06F8/41G06F8/52G06F21/64
    • The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.
    • 本文提供的技术涉及保护已经优化的原始代码的完整性。 例如,处理器可以执行取出操作以从存储器获得指定的代码。 在执行期间,代码可以被优化并存储在存储器的一部分中。 处理器可以从存储器的一部分获得优化的代码。 可以修改第一表的条目以指示特定代码和优化的代码之间的关系。 可以修改第二表的一个或多个条目以指定一个或多个物理存储器位置。 第二表中的一个或多个条目中的每一个可对应于第一表的条目。 当第二表的一个或多个条目中的每一个有效时,处理器可以执行优化的代码。
    • 7. 发明申请
    • A BALANCED P-LRU TREE FOR A
    • 一个平衡的P-LRU树,一个“多个3”的方式高速缓存
    • WO2013095467A1
    • 2013-06-27
    • PCT/US2011/066652
    • 2011-12-21
    • INTEL CORPORATIONBASEL, AdiHILDESHEIM, GurRAIKIN, ShlomoCHAPPELL, RobertKIM, Ho-SeopBHATIA, Rohit
    • BASEL, AdiHILDESHEIM, GurRAIKIN, ShlomoCHAPPELL, RobertKIM, Ho-SeopBHATIA, Rohit
    • G06F1/00
    • G06F12/122G06F3/0604G06F12/00G06F12/0842G06F12/0864G06F12/124G06F12/125
    • In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a "multiple of 3" number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N-1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a "multiple of 5" number of cache ways, and variations of the "multiple of 3" number of cache ways.
    • 根据本文公开的实施例,提供了用于实现用于“3”倍的方式高速缓存的平衡P-LRU树的方法,系统,机制,技术和装置。 例如,在一个实施例中,这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中,多个方式包括一个数量是三的倍数,而不是二的幂,并且其中多个方式被组织成多对。 在这样的实施例中,装置还包括用于多个对中的每一对的单个位,其中每个单个位将用作表示相关联的方式的中间级决策节点和具有正好两个单独位的根级判定节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中,总数是N-1,其中N是多个方式的总路数。 还提供了替代结构,用于完整的LRU实现,“多路复用5”缓存方式,以及“3”倍数缓存方式的变化。
    • 10. 发明申请
    • METHODS AND APPARATUS FOR EFFICIENT COMMUNICATION BETWEEN CACHES IN HIERARCHICAL CACHING DESIGN
    • 用于分层缓存设计中的高速缓存之间的有效通信的方法和设备
    • WO2013095640A1
    • 2013-06-27
    • PCT/US2011/067217
    • 2011-12-23
    • INTEL CORPORATIONSHALEV, RonGILAD, YiftachRAIKIN, ShlomoYANOVER, IgorSHWARTSMAN, StanislavSADE, Raanan
    • SHALEV, RonGILAD, YiftachRAIKIN, ShlomoYANOVER, IgorSHWARTSMAN, StanislavSADE, Raanan
    • G06F13/14G06F13/38G06F12/08
    • G06F12/0811G06F12/08G06F12/0844G06F12/0897G06F13/14G06F13/38
    • In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.
    • 根据本文公开的实施例,提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法,系统,机制,技术和装置。 例如,在一个实施例中,这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。 这种实施例中的数据缓冲器与数据总线可通信地接口,并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线,一个或多个控制位以指示各个数据缓冲器的状态,以及 与完整缓存行相关联的地址。 在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态以及与相应无数据缓冲器相关联的高速缓存间传输线的地址。 在这样的实施例中,高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线,并且进一步将数据总线上的缓存间传输线写入低级缓存。