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1. 发明申请

WO2010077885A3 EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA 审中-公开
标题翻译：扩展缓存协议来支持本地缓存数据
公开(公告)号：WO2010077885A3
公开(公告)日：2010-10-07
申请号：PCT/US2009068121
申请日：2009-12-15
申请人： INTEL CORP , SHEAFFER GAD , RAIKIN SHLOMO , BASSIN VADIM , COHEN EHUD , MARGULIS OLEG , SADE RAANAN
发明人： SHEAFFER GAD , RAIKIN SHLOMO , BASSIN VADIM , COHEN EHUD , MARGULIS OLEG , SADE RAANAN
IPC分类号： G06F9/06 , G06F5/00 , G06F9/46 , G06F12/00
CPC分类号： G06F9/3834 , G06F9/467 , G06F12/0831 , G06F12/084
摘要： A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.
摘要翻译：这里描述了用于扩展高速缓存一致性以保存缓冲数据以支持事务执行的方法和装置。以缓冲的方式执行引用与数据项相关联的地址的事务存储操作。这里，与保存数据项的高速缓存行相关联的一致性状态被转换到缓冲状态。响应缓冲数据项的本地请求，提供数据项以确保内部事务顺序排序。然而，响应于外部访问请求，提供了错误响应以确保事务更新的数据项在提交之前不会被全局可见。一旦提交，缓存的行将转换到修改状态，使数据项全局可见。

2. 发明申请

WO2013101125A1 PROTECTING THE INTEGRITY OF BINARY TRANSLATED CODE 审中-公开
标题翻译：保护二进制翻译代码的完整性
公开(公告)号：WO2013101125A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067974
申请日：2011-12-29
申请人： INTEL CORPORATION , RAIKIN, Shlomo , RAPPOPORT, Lihu , NUZMAN, Joseph
发明人： RAIKIN, Shlomo , RAPPOPORT, Lihu , NUZMAN, Joseph
IPC分类号： G06F9/30 , G06F9/305 , G06F15/80 , G06F13/38
CPC分类号： G06F8/41 , G06F8/52 , G06F21/64
摘要： The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.
摘要翻译：本文提供的技术涉及保护已经优化的原始代码的完整性。例如，处理器可以执行取出操作以从存储器获得指定的代码。在执行期间，代码可以被优化并存储在存储器的一部分中。处理器可以从存储器的一部分获得优化的代码。可以修改第一表的条目以指示特定代码和优化的代码之间的关系。可以修改第二表的一个或多个条目以指定一个或多个物理存储器位置。第二表中的一个或多个条目中的每一个可对应于第一表的条目。当第二表的一个或多个条目中的每一个有效时，处理器可以执行优化的代码。

3. 发明申请

WO2013095475A1 APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTION 审中-公开
标题翻译：用于记忆级别生产者消费者指令的装置和方法
公开(公告)号：WO2013095475A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066674
申请日：2011-12-21
申请人： INTEL CORPORATION , RAIKIN, Shlomo , SADE, Raanan , VALENTINE, Robert , MANDELBLAT, Julius Yuli , SHALEV, Ron , NOVAKOVSKY, Larisa
发明人： RAIKIN, Shlomo , SADE, Raanan , VALENTINE, Robert , MANDELBLAT, Julius Yuli , SHALEV, Ron , NOVAKOVSKY, Larisa
IPC分类号： G06F13/14 , G06F13/38 , G06F9/30
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3881 , G06F12/0866 , G06F13/1673 , G06F13/38 , G06T1/20 , G06T1/60 , G09G5/006
摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.
摘要翻译：描述了一种有效地将数据从中央处理单元（CPU）的核心传输到图形处理单元（GPU）的装置和方法。例如，一种方法的一个实施例包括：将数据写入CPU的核心内的缓冲器，直到指定的数据量被写入为止; 在检测到指定量的数据已被写入时，响应地产生驱逐周期，驱逐循环使数据从缓冲器传送到可由核心和GPU访问的高速缓存; 设置指示以向GPU指示数据在高速缓存中可用; 并且在GPU检测到指示时，在从GPU接收到读取信号时，从高速缓存提供数据给GPU。

4. 发明申请

WO2012040425A2 REGULATING ATOMIC MEMORY OPERATIONS TO PREVENT DENIAL OF SERVICE ATTACK 审中-公开
标题翻译：规范原子内存操作以防止服务攻击拒绝
公开(公告)号：WO2012040425A2
公开(公告)日：2012-03-29
申请号：PCT/US2011052696
申请日：2011-09-22
申请人： INTEL CORP , BAIR MICHAEL S , ONG LESLIE A , TUCKNOTT MICHAEL D , BURNS DAVID W , RAGHUVANSHI PANKAJ , YANOVER IGOR , CHAPPELL ROBERT S , RAIKIN SHLOMO , MATH PRAKASH , SADE RAANAN
发明人： BAIR MICHAEL S , ONG LESLIE A , TUCKNOTT MICHAEL D , BURNS DAVID W , RAGHUVANSHI PANKAJ , YANOVER IGOR , CHAPPELL ROBERT S , RAIKIN SHLOMO , MATH PRAKASH , SADE RAANAN
IPC分类号： G06F15/76 , G06F12/00 , G06F13/14
CPC分类号： G06F9/526
摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，将定时器与第一线程相关联，并且在完成第一线程之后阻止第一线程执行存储器群集操作原子内存操作，直到预防窗口过去。在一些实施例中，该方法可以由与处理器的存储器执行单元相关联的调节逻辑来执行。描述并要求保护其他实施例。

5. 发明申请

WO2014105167A1 APPARATUS AND METHOD FOR PAGE WALK EXTENSION FOR ENHANCED SECURITY CHECKS 审中-公开
标题翻译：用于增强安全检查的页面扩展的装置和方法
公开(公告)号：WO2014105167A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047423
申请日：2013-06-24
申请人： INTEL CORPORATION , HILDESHEIM, Gur , ANATI, Ittai , SHAIF, Hisham , RAIKIN, Shlomo , GERZON, Gideon , SAVAGAONKAR, Uday R. , ROZAS, Carlos V. , MCKEEN, Francis X. , GOLDSMITH, Michael A. , DEWAN, Prashant
发明人： HILDESHEIM, Gur , ANATI, Ittai , SHAIF, Hisham , RAIKIN, Shlomo , GERZON, Gideon , SAVAGAONKAR, Uday R. , ROZAS, Carlos V. , MCKEEN, Francis X. , GOLDSMITH, Michael A. , DEWAN, Prashant
IPC分类号： G06F21/78
CPC分类号： G06F12/145 , G06F12/084 , G06F12/1027 , G06F12/1483 , G06F21/53
摘要： An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.
摘要翻译：一种用于由处理器管理保护表的装置和方法。例如，根据本发明的一个实施例的处理器包括：保护表管理逻辑，用于管理保护表，所述保护表具有每个受保护页面的条目或存储器中的每组受保护页面; 其中保护表管理逻辑防止用户应用程序代码和操作系统程序代码直接访问保护表，但允许处理器直接访问。

6. 发明申请

WO2014004151A2 VIRTUAL MEMORY ADDRESS RANGE REGISTER 审中-公开
标题翻译：虚拟内存地址范围注册
公开(公告)号：WO2014004151A2
公开(公告)日：2014-01-03
申请号：PCT/US2013/046169
申请日：2013-06-17
申请人： INTEL CORPORATION , HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SAVAGAONKAR, Uday , MCKEEN, Francis , ROZAS, Carlos , GOLDSMITH, Michael , DEWAN, Prashant
发明人： HILDESHEIM, Gur , RAIKIN, Shlomo , ANATI, Ittai , GERZON, Gideon , SAVAGAONKAR, Uday , MCKEEN, Francis , ROZAS, Carlos , GOLDSMITH, Michael , DEWAN, Prashant
IPC分类号： G06F12/08
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

7. 发明申请

WO2013095467A1 A BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE 审中-公开
标题翻译：一个平衡的P-LRU树，一个“多个3”的方式高速缓存
公开(公告)号：WO2013095467A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066652
申请日：2011-12-21
申请人： INTEL CORPORATION , BASEL, Adi , HILDESHEIM, Gur , RAIKIN, Shlomo , CHAPPELL, Robert , KIM, Ho-Seop , BHATIA, Rohit
发明人： BASEL, Adi , HILDESHEIM, Gur , RAIKIN, Shlomo , CHAPPELL, Robert , KIM, Ho-Seop , BHATIA, Rohit
IPC分类号： G06F1/00
CPC分类号： G06F12/122 , G06F3/0604 , G06F12/00 , G06F12/0842 , G06F12/0864 , G06F12/124 , G06F12/125
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a "multiple of 3" number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N-1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a "multiple of 5" number of cache ways, and variations of the "multiple of 3" number of cache ways.
摘要翻译：根据本文公开的实施例，提供了用于实现用于“3”倍的方式高速缓存的平衡P-LRU树的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。在这样的实施例中，多个方式包括一个数量是三的倍数，而不是二的幂，并且其中多个方式被组织成多对。在这样的实施例中，装置还包括用于多个对中的每一对的单个位，其中每个单个位将用作表示相关联的方式的中间级决策节点和具有正好两个单独位的根级判定节点指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

8. 发明申请

WO2010077842A2 METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE 审中-公开
标题翻译：用于在硬件中保存损失元数据的地形空间
公开(公告)号：WO2010077842A2
公开(公告)日：2010-07-08
申请号：PCT/US2009067983
申请日：2009-12-15
申请人： INTEL CORP , SHAEFFER GAD , RAIKIN SHLOMO , BASSIN VADIM , SADE RAANAN , COHEN EHUD , MARGULIS OLEG
发明人： SHAEFFER GAD , RAIKIN SHLOMO , BASSIN VADIM , SADE RAANAN , COHEN EHUD , MARGULIS OLEG
IPC分类号： G06F9/06 , G06F9/46 , G06F12/00
CPC分类号： G06F12/0615 , G06F9/467 , G06F12/0842 , G06F12/1027
摘要： A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.
摘要翻译：这里描述用于保存有损元数据的形而上学地址空间的方法和装置。遇到引用数据项的数据地址的显式或隐式元数据访问操作。硬件将数据地址修改为包括形而上学扩展的元数据地址。形而上学扩展覆盖了数据地址空间上的一个或多个形而上学地址空间。使用包括形而上学扩展的元数据地址的一部分来搜索保存数据项的高速缓冲存储器的标签阵列。因此，元数据访问操作仅基于元数据地址扩展名来命中高速缓存的元数据条目。然而，随着元数据被保存在高速缓存中，元数据可能与高速缓存中的空间的数据竞争。

9. 发明申请

WO2014105151A1 APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB) 审中-公开
标题翻译：多页翻页预处理缓存器（TLB）的设备和方法
公开(公告)号：WO2014105151A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046910
申请日：2013-06-20
申请人： INTEL CORPORATION , RAIKIN, Shlomo , HAMAMA, Oren , CHAPPELL, Robert S. , RUST, Camron B. , LUU, Han S. , ONG, Leslie A. , HILDESHEIM, Gur
发明人： RAIKIN, Shlomo , HAMAMA, Oren , CHAPPELL, Robert S. , RUST, Camron B. , LUU, Han S. , ONG, Leslie A. , HILDESHEIM, Gur
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , Y02D10/13
摘要： An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.
摘要翻译：一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。

10. 发明申请

WO2013095640A1 METHODS AND APPARATUS FOR EFFICIENT COMMUNICATION BETWEEN CACHES IN HIERARCHICAL CACHING DESIGN 审中-公开
标题翻译：用于分层缓存设计中的高速缓存之间的有效通信的方法和设备
公开(公告)号：WO2013095640A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067217
申请日：2011-12-23
申请人： INTEL CORPORATION , SHALEV, Ron , GILAD, Yiftach , RAIKIN, Shlomo , YANOVER, Igor , SHWARTSMAN, Stanislav , SADE, Raanan
发明人： SHALEV, Ron , GILAD, Yiftach , RAIKIN, Shlomo , YANOVER, Igor , SHWARTSMAN, Stanislav , SADE, Raanan
IPC分类号： G06F13/14 , G06F13/38 , G06F12/08
CPC分类号： G06F12/0811 , G06F12/08 , G06F12/0844 , G06F12/0897 , G06F13/14 , G06F13/38
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.
摘要翻译：根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及与完整缓存行相关联的地址。在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态以及与相应无数据缓冲器相关联的高速缓存间传输线的地址。在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。

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