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1. 发明申请

WO2005098624A1 A METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING 审中-公开
标题翻译：提供用户级多媒体的方法和系统
公开(公告)号：WO2005098624A1
公开(公告)日：2005-10-20
申请号：PCT/US2005/010923
申请日：2005-03-31
申请人： INTEL CORPORATION , GROCHOWSKI, Edward, T. , WANG, Hong , SHEN, John, P. , WANG, Perry, H. , COLLINS, Jamison, D. , HELD, James, P. , KUNDU, Partha , LEVIATHAN, Raya , NGAI, Tin-Fook
发明人： GROCHOWSKI, Edward, T. , WANG, Hong , SHEN, John, P. , WANG, Perry, H. , COLLINS, Jamison, D. , HELD, James, P. , KUNDU, Partha , LEVIATHAN, Raya , NGAI, Tin-Fook
IPC分类号： G06F9/46
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译：公开了一种提供用户级多线程的方法和系统。根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

2. 发明申请

WO2015196413A1 MEMCACHED SYSTEMS HAVING LOCAL CACHES 审中-公开
标题翻译：具有本地缓存的备用系统
公开(公告)号：WO2015196413A1
公开(公告)日：2015-12-30
申请号：PCT/CN2014/080824
申请日：2014-06-26
申请人： INTEL CORPORATION , WU, Xiangbin , ZHU, Shunyu , SHEN, Yingzhe , NGAI, Tin-Fook
发明人： WU, Xiangbin , ZHU, Shunyu , SHEN, Yingzhe , NGAI, Tin-Fook
IPC分类号： G06F17/30
CPC分类号： H04L67/2852 , G06F17/30902 , H04L67/10 , H04L67/42
摘要： Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a client device of the memcached system may include memory and one or more processors coupled with the memory. Further, the client device may include memcached logic configured to receive a request to Get or Set a value corresponding to a key in the memcached system, determine, in response to the receive, whether the key results in a hit in a local cache maintained in memory by the memcached logic, and service the Get or Set request based at least in part on whether a result of the determine indicates the key results in a hit in the local cache. In embodiments, a server of the memcached system may include complement memcached logic to server a Get, Set or an Update request. Other embodiments may be described and/or claimed.
摘要翻译：本文公开了与memcached系统相关联的装置，方法和存储介质。在实施例中，memcached系统的客户端设备可以包括存储器和与存储器耦合的一个或多个处理器。此外，客户端设备可以包括被配置为接收获取或设置与memcached系统中的密钥对应的值的请求的memcached逻辑，响应于接收确定密钥是否导致本地高速缓存中的命中被保持在存储器通过memcached逻辑，并且至少部分地基于确定的结果是否指示在本地高速缓存中的命中的关键结果来服务Get或Set请求。在实施例中，memcached系统的服务器可以包括用于服务Get，Set或Update请求的补码memcached逻辑。可以描述和/或要求保护其他实施例。

3. 发明申请

WO2013123670A1 COOPERATIVE RADIO ACCESS NETWORK WITH CENTRALIZED BASE STATION BASEBAND UNIT (BBU) PROCESSING POOL 审中-公开
标题翻译：合作无线电接入网络与中央基站基站（BBU）处理池
公开(公告)号：WO2013123670A1
公开(公告)日：2013-08-29
申请号：PCT/CN2012/071572
申请日：2012-02-24
申请人： LI, Guangjie , YANG, Xuebin , ZHANG, Senjie , NGAI, Tin-Fook
发明人： LI, Guangjie , YANG, Xuebin , ZHANG, Senjie , NGAI, Tin-Fook
IPC分类号： H04W28/08 , H04W88/08
CPC分类号： H04W28/08 , H04W88/085
摘要： Embodiments of an enhanced Node B (e NB) configured for use in a cooperative radio access networks (C-RAN) and method for central baseband unit (BBU) processing are generally described herein. In some embodiments, the eNB may include a baseband unit (BBU) processing pool comprising a plurality of processing units. The BBU processing pool is configured to share the processing load of several sectors. A control unit may monitor the processing load of the processing units and perform dynamic load sharing by migrating the baseband processing between the processing units without changing a carrier used by user equipment operating with a sector.
摘要翻译：在此通常描述配置用于协作无线电接入网络（C-RAN）中的增强型节点B（e NB）和用于中央基带单元（BBU）处理的方法）的实施例。在一些实施例中，eNB可以包括包括多个处理单元的基带单元（BBU）处理池。 BBU处理池被配置为共享几个扇区的处理负载。控制单元可以通过在处理单元之间迁移基带处理来监视处理单元的处理负荷并执行动态负载共享，而不改变由扇区操作的用户设备使用的载波。

4. 发明申请

WO2015096001A1 SYSTEM-ON-A-CHIP (SOC) INCLUDING HYBRID PROCESSOR CORES 审中-公开
标题翻译：系统在线（SOC），包括混合处理器线
公开(公告)号：WO2015096001A1
公开(公告)日：2015-07-02
申请号：PCT/CN2013/090225
申请日：2013-12-23
申请人： INTEL CORPORATION , CHEN, Hu Tiger , CHEN, Liang , LIN, Chunxiao , LUO, Sai , TIAN, Hai Ge , WANG, Rui Gang , NGAI, Tin-Fook
发明人： CHEN, Hu Tiger , CHEN, Liang , LIN, Chunxiao , LUO, Sai , TIAN, Hai Ge , WANG, Rui Gang , NGAI, Tin-Fook
IPC分类号： G06F9/45
CPC分类号： G06F15/80 , G06F9/46 , G06F13/4027 , G06F13/4068 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A processing device includes a first processor module comprising a first core designed according to a first instruction set (ISA), and a second processor module comprising a second core designed according to a second ISA. The first and second processor modules are fabricated on a same die.
摘要翻译：一种处理装置包括：第一处理器模块，包括根据第一指令集（ISA）设计的第一核心;以及第二处理器模块，包括根据第二ISA设计的第二核心。第一和第二处理器模块被制造在相同的芯片上。

5. 发明申请

WO2014063323A1 PARTIAL VECTORIZATION COMPILATION SYSTEM 审中-公开
标题翻译：部分矢量编译系统
公开(公告)号：WO2014063323A1
公开(公告)日：2014-05-01
申请号：PCT/CN2012/083476
申请日：2012-10-25
申请人： INTEL CORPORATION , NGAI, Tin-Fook , LIN, Chunxiao , SHEN, Yingzhe , ZHANG, Chao
发明人： NGAI, Tin-Fook , LIN, Chunxiao , SHEN, Yingzhe , ZHANG, Chao
IPC分类号： G06F9/45
CPC分类号： G06F9/30036 , G06F8/433 , G06F8/4441 , G06F8/452
摘要： Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.
摘要翻译：通常，本公开提供了用于生成和执行部分向量化代码的技术，其可以包括要被矢量化的代码的循环体内的后向依赖性。该方法可以包括识别代码的循环体内的后向依赖性; 在所述循环体内选择一个或多个迭代范围，其中所选择的范围排除所识别的后向依赖性; 并对所选范围进行向量化。该系统可以包括被配置为提供预测向量指令执行，循环迭代范围使能和动态循环依赖性检查的向量处理器。

6. 发明申请

WO2012087561A2 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 审中-公开
标题翻译：用于硬件和软件系统的系统，设备和方法，用于自动将程序分解成多个并行线程
公开(公告)号：WO2012087561A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/063466
申请日：2011-12-06
申请人： INTEL CORPORATION , SAGER, David J. , SASANKA, Ruchira , GABOR, Ron , RAIKIN, Shlomo , NUZMAN, Joseph , PELED, Leeor , DOMER, Jason A. , KIM, Ho-Seop , WU, Youfeng , YAMADA, Koichi , NGAI, Tin-Fook , CHEN, Howard H. , BOBBA, Jayaram , COOK, Jeffrey J. , SHAIKH, Osmar M. , SRINIVAS, Suresh
发明人： SAGER, David J. , SASANKA, Ruchira , GABOR, Ron , RAIKIN, Shlomo , NUZMAN, Joseph , PELED, Leeor , DOMER, Jason A. , KIM, Ho-Seop , WU, Youfeng , YAMADA, Koichi , NGAI, Tin-Fook , CHEN, Howard H. , BOBBA, Jayaram , COOK, Jeffrey J. , SHAIKH, Osmar M. , SRINIVAS, Suresh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

7. 发明申请

WO2013147869A1 APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COUMPUTATION 审中-公开
标题翻译：选择矢量图选择元素的装置和方法
公开(公告)号：WO2013147869A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031596
申请日：2012-03-30
申请人： INTEL CORPORATION , LEE, Victor W. , BHARADWAJ, Jayashankar , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara
发明人： LEE, Victor W. , BHARADWAJ, Jayashankar , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara
IPC分类号： G06F1/00 , G06F9/06 , G06F9/302
CPC分类号： G06F7/548 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3877 , G06F9/3895
摘要： An apparatus and method are described for performing a vector reduction. For example, an apparatus according to one embodiment comprises: a reduction logic tree comprised of a set of N- l reduction logic blocks used to perform reduction in a single operation cycle for N vector elements; a first input vector register storing a first input vector communicatively Coupled to the set of reduction logic blocks; a second input vector register storing a second input vector communicatively coupled to the set of reduction logic blocks; a mask register storing a mask value controlling a set of one or more multiplexers, each of the set of multiplexers selecting a value directly from the first input vector register or an output containing a processed value from one of the reduction logic blocks; and an output vector register coupled to outputs of the one or more multiplexers to receive values output passed through by each of the multiplexers responsive to the control signals.
摘要翻译：描述了用于执行向量减少的装置和方法。例如，根据一个实施例的装置包括：还原逻辑树，包括用于对N个向量元素执行单个操作周期的减少的一组N-1个减少逻辑块; 第一输入向量寄存器，其以通信方式存储耦合到所述一组还原逻辑块的第一输入向量; 存储通信地耦合到所述一组减少逻辑块的第二输入向量的第二输入向量寄存器; 屏蔽寄存器，其存储控制一个或多个多路复用器的集合的掩码值，所述多路复用器集合中的每一个直接从所述第一输入向量寄存器选择值，或者包含来自所述还原逻辑块之一的处理值的输出; 以及耦合到所述一个或多个多路复用器的输出的输出矢量寄存器，以响应于所述控制信号接收由所述多路复用器中的每一个通过的值。

8. 发明申请

WO2013095608A1 APPARATUS AND METHOD FOR VECTORIZATION WITH SPECULATION SUPPORT 审中-公开
标题翻译：用于带有参数支持的矢量化的装置和方法
公开(公告)号：WO2013095608A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067085
申请日：2011-12-23
申请人： INTEL CORPORATION , BHARADWAJ, Jayashankar , LEE, Victor W. , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara, S.
发明人： BHARADWAJ, Jayashankar , LEE, Victor W. , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara, S.
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F11/0751 , G06F9/30018 , G06F9/30036 , G06F9/30043
摘要： An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
摘要翻译：描述了用于检测和响应处理器中的故障状况的装置和方法。例如，一种方法的一个实施例包括：从第一向量寄存器连续读取每个有源元件，每个有源元件指定用于集合或加载操作的地址; 检测与一个或多个所述有源元件相关联的一个或多个故障状况; 对于在除了所述第一有源元件之外的元件的检测到的故障状况之前连续读取的每个有源元件，将从与所述有源元件相关联的地址加载的数据存储在第一输出向量寄存器中; 并且对于与检测到的故障状况相关联的每个有源元件并且在检测到的故障状况之后，将输出屏蔽寄存器中的位设置为指示检测到的故障状况。

9. 发明申请

WO2016045059A1 MULTICORE MEMORY DATA RECORDER FOR KERNEL MODULE 审中-公开
标题翻译：用于KERNEL模块的MULTICORE MEMORY DATA RECORDER
公开(公告)号：WO2016045059A1
公开(公告)日：2016-03-31
申请号：PCT/CN2014/087447
申请日：2014-09-25
申请人： INTEL CORPORATION , LUO, Sai , NGAI, Tin-Fook , CHEN, Hu , ZHOU, Xiaocheng , LIN, Chunxiao , ZHAO, Kang
发明人： LUO, Sai , NGAI, Tin-Fook , CHEN, Hu , ZHOU, Xiaocheng , LIN, Chunxiao , ZHAO, Kang
IPC分类号： G06F15/167
CPC分类号： G06F12/0842 , G06F11/36 , G06F11/3632 , G06F12/0831 , G06F12/0833 , G06F12/0875 , G06F2212/1016 , G06F2212/1032 , G06F2212/452 , G06F2212/621
摘要： A processing deviceincludes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitoredand a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record andrecord the memory address in a second record.
摘要翻译：处理设备包括耦合到存储器的处理核，以执行包括被识别为被监视的代码段的任务和经由核心接口耦合到处理核的内核记录器。内核记录器包括第一过滤器电路，用于响应于确定正在执行的任务进入代码段，将内核记录器设置为第一模式，在第一模式下，内核记录器将在第一记录中记录访问的多个存储器地址通过代码段，并且响应于确定任务的执行退出代码段，将内核记录器设置为第二模式，在该第二模式下，内核记录器将检测对记录在第一记录中的存储器地址的写操作，并记录第二个记录中的内存地址。

10. 发明申请

WO2013095642A1 SYSTEMS, APPARATUSES, AND METHODS FOR SETTING AN OUTPUT MASK IN A DESTINATION WRITEMASK REGISTER FROM A SOURCE WRITE MASK REGISTER USING AN INPUT WRITEMASK AND IMMEDIATE 审中-公开
标题翻译：用于使用输入写入和立即从源写入掩码寄存器设置目的地写入寄存器中的输出掩码的系统，设备和方法
公开(公告)号：WO2013095642A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067219
申请日：2011-12-23
申请人： INTEL CORPORATION , LEE, Victor, W. , KIM, Daehyun , NGAI, Tin-fook , BHARADWAJ, Jayashankar , HARTONO, Albert , BAGHSORKHI, Sara , VASUDEVAN, Nalini
发明人： LEE, Victor, W. , KIM, Daehyun , NGAI, Tin-fook , BHARADWAJ, Jayashankar , HARTONO, Albert , BAGHSORKHI, Sara , VASUDEVAN, Nalini
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30025 , G06F9/30072 , G06F15/8007 , G06F15/8053 , G06F15/8084 , G06F15/8092
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.
摘要翻译：描述了用于在计算机处理器中执行基于向量比较响应于单个指令生成谓词掩码的系统，装置和方法的实施例。

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