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    • 1. 发明申请
      US20100242006A1 METHOD OF TIMING CRITICALITY CALCULATION FOR STATISTICAL TIMING OPTIMIZATION OF VLSI CIRCUIT 有权
    • METHOD OF TIMING CRITICALITY CALCULATION FOR STATISTICAL TIMING OPTIMIZATION OF VLSI CIRCUIT
    • 定时关键度计算方法对VLSI电路的统计时序优化
    • US20100242006A1
    • 2010-09-23
    • US12474547
    • 2009-05-29
    • Hyoun Soo Park , Young Hwan Kim , Dai Joon Hyun , Wook Kim
    • Hyoun Soo Park , Young Hwan Kim , Dai Joon Hyun , Wook Kim
    • G06F17/10
    • G06F17/5031 , G06F17/505
    • Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.
    • 提供了一种优化积分电路的统计定时的方法，该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化，以ADD操作和基于块的统计静态的MAX操作 时序分析（SSTA）方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值，计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此，基于统计静态时序分析（SSTA）的ADD操作和MAX操作的线性近似来计算定时收益关键性，因此计算复杂度相对于总节点数是线性的，关键节点显着影响定时收益 可以更准确地提取电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US08046724B2 Method of timing criticality calculation for statistical timing optimization of VLSI circuit 有权
    • Method of timing criticality calculation for statistical timing optimization of VLSI circuit
    • VLSI电路统计时序优化的定时临界计算方法
    • US08046724B2
    • 2011-10-25
    • US12474547
    • 2009-05-29
    • Hyoun Soo Park , Young Hwan Kim , Dai Joon Hyun , Wook Kim
    • Hyoun Soo Park , Young Hwan Kim , Dai Joon Hyun , Wook Kim
    • G06F9/455 , G06F17/50
    • G06F17/5031 , G06F17/505
    • Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.
    • 提供了一种优化集成电路的统计定时的方法，该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化，以ADD操作和基于块的统计静态的MAX操作 时序分析（SSTA）方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值，计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此，基于统计静态时序分析（SSTA）的ADD操作和MAX操作的线性近似来计算定时收益关键性，因此计算复杂度相对于总节点数是线性的，关键节点显着影响定时收益 可以更准确地提取电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US08046725B2 Method of incremental statistical static timing analysis based on timing yield 有权
    • Method of incremental statistical static timing analysis based on timing yield
    • 基于定时收益的增量统计静态时序分析方法
    • US08046725B2
    • 2011-10-25
    • US12475545
    • 2009-05-31
    • Jinwook Kim , Young Hwan Kim , Wook Kim
    • Jinwook Kim , Young Hwan Kim , Wook Kim
    • G06F9/455 , G06F17/50
    • G06F17/5031 , G06F2217/84
    • Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.
    • 提供了数字电路的增量SSTA（统计静态时序分析）的方法，该方法包括第一步骤，其中当在数字电路中替换门时，从更换的门的节点执行延迟传播 基于SSTA的虚拟汇聚节点; 第二步骤，如果在向虚拟汇聚节点传播延迟的每个门的门定时收益的改变值小于预定阈值，则停止相对于相应门的扇出门的延迟传播; 以及第三步骤，当相对于所替换的门的节点的延迟传播到虚拟宿节点时，在虚拟宿节点处计算新的定时收益。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US08156460B2 Method of estimating a leakage current in a semiconductor device 有权
    • Method of estimating a leakage current in a semiconductor device
    • 估计半导体器件中漏电流的方法
    • US08156460B2
    • 2012-04-10
    • US12547729
    • 2009-08-26
    • Kyung-Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
    • Kyung-Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
    • G06F17/50
    • G06F17/5036
    • In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.
    • 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际泄漏特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中所有单元的虚拟单元泄漏特性函数进行算术运算，产生段的段泄漏特性函数。 然后，通过统计操作芯片中所有段的段泄漏特性函数来产生芯片的全芯片泄漏特性功能。 因此，Wilkinson用于产生全芯片泄漏特性功能的方法的计算负载可以显着降低。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明申请
      US20100306724A1 METHOD OF INCREMENTAL STATISTICAL STATIC TIMING ANALYSIS BASED ON TIMING YIELD 有权
    • METHOD OF INCREMENTAL STATISTICAL STATIC TIMING ANALYSIS BASED ON TIMING YIELD
    • 基于时序的增量统计静态时序分析方法
    • US20100306724A1
    • 2010-12-02
    • US12475545
    • 2009-05-31
    • Jinwook Kim , Young Hwan Kim , Wook Kim
    • Jinwook Kim , Young Hwan Kim , Wook Kim
    • G06F17/50
    • G06F17/5031 , G06F2217/84
    • Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.
    • 提供了数字电路的增量SSTA（统计静态时序分析）的方法，该方法包括第一步骤，其中当在数字电路中替换门时，从更换的门的节点执行延迟传播 基于SSTA的虚拟汇聚节点; 第二步骤，如果在向虚拟汇聚节点传播延迟的每个门的门定时收益的改变值小于预定阈值，则停止相对于相应门的扇出门的延迟传播; 以及第三步骤，当相对于所替换的门的节点的延迟传播到虚拟宿节点时，在虚拟宿节点处计算新的定时收益。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20100058258A1 Method of Estimating a Leakage Current in a Semiconductor Device 有权
    • Method of Estimating a Leakage Current in a Semiconductor Device
    • 估算半导体器件中泄漏电流的方法
    • US20100058258A1
    • 2010-03-04
    • US12547729
    • 2009-08-26
    • Kyung Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
    • Kyung Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
    • G06F17/50
    • G06F17/5036
    • In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.
    • 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际漏电特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中每个单元的虚拟单元泄漏特性函数进行算术运算来产生段泄漏特性函数。 然后，通过统计操作芯片中每个段的段泄漏特性函数来产生全片泄漏特性函数。 因此，威尔金森的用于产生全芯片泄漏特性函数的方法的计算量可以显着降低。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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