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1. 发明授权

US08013628B2 Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same 有权
标题翻译：具有有源时钟屏蔽结构的电路和包括其的半导体集成电路
公开(公告)号：US08013628B2
公开(公告)日：2011-09-06
申请号：US12381431
申请日：2009-03-12
申请人： Bong-Hyun Lee , Jung-Yun Choi , Jae-Han Jeon , Kyung-Tae Do
发明人： Bong-Hyun Lee , Jung-Yun Choi , Jae-Han Jeon , Kyung-Tae Do
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04B15/02 , H04B2215/064
摘要： A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.
摘要翻译：具有有源时钟屏蔽结构的电路包括接收时钟信号并基于时钟信号执行逻辑运算的逻辑电路，基于时钟信号切换逻辑电路的模式的功率门控电路，基于电源门控信号，将时钟信号发送到逻辑电路的时钟信号传输线，以及至少一个电源门控信号传输线，其将电源门控信号发送到电源门控电路并用作与时钟的屏蔽线对信号传输线。

2. 发明申请

US20080141201A1 BLACK BOX TIMING MODELING METHOD AND COMPUTER SYSTEM FOR LATCH-BASED SUBSYSTEM 有权
标题翻译：基于LATCH的子系统的黑盒时序建模方法和计算机系统
公开(公告)号：US20080141201A1
公开(公告)日：2008-06-12
申请号：US11934252
申请日：2007-11-02
申请人： Kyung Tae DO , Young Hwan KIM , Haeng Seon SON
发明人： Kyung Tae DO , Young Hwan KIM , Haeng Seon SON
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input connected to the synchronous element and forming the setup time arc using the extracted setup time; and characterizing a clock-to-output delay arc by providing information on an output departure time from an output based on a rising or falling edge of a clock of a closest synchronous element connected to the output, at least partially based on the setup time arc and forming the clock-to-output delay arc. Accordingly, the method can be efficiently used for a latch-based design without re-verifying internal components of the latch-based design during an upper-level verification, thereby reducing verification time and model size.
摘要翻译：提供了一种用于数字电路的黑盒定时建模方法，包括具有锁存器的同步元件。该方法包括：通过相对于连接到同步元件的输入提取相对于同步元件的时钟的上升沿或下降沿的建立时间来表征建立时间弧，并使用所提取的建立时间来形成建立时间弧 ; 以及通过基于建立时间弧至少部分地基于连接到输出的最近同步元件的时钟的上升沿或下降沿从输出提供关于输出离开时间的信息来表征时钟到输出延迟弧并形成时钟到输出的延迟电弧。因此，该方法可以有效地用于基于锁存器的设计，而不会在上级验证期间重新验证基于锁存器的设计的内部部件，从而减少验证时间和型号尺寸。

3. 发明授权

US08621399B2 Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices 失效
标题翻译：设计半导体器件的方法和修改半导体器件布局的方法
公开(公告)号：US08621399B2
公开(公告)日：2013-12-31
申请号：US13458516
申请日：2012-04-27
申请人： Kyung-Tae Do , Yong-Seok Lee , Hyo-Sig Won , Jung-Yun Choi , Jong-Ho Kim
发明人： Kyung-Tae Do , Yong-Seok Lee , Hyo-Sig Won , Jung-Yun Choi , Jong-Ho Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.
摘要翻译：在设计半导体器件的方法中，可以选择包括在半导体器件的布局中的晶体管。可以设置偏置数据以改变所选择的晶体管的特性。可以在忽略偏置数据之后执行用于半导体器件的布局的设计规则检查（DRC）处理。可以基于偏置数据执行用于半导体器件的布局的光学邻近校正（OPC）处理。

4. 发明申请

US20120313693A1 SEMICONDUCTOR DEVICE, METHOD AND SYSTEM WITH LOGIC GATE REGION RECEIVING CLOCK SIGNAL AND BODY BIAS VOLTAGE BY ENABLE SIGNAL 审中-公开
标题翻译：半导体器件，具有逻辑门控区域的接收时钟信号的方法和系统和通过使能信号进行的体虚电压
公开(公告)号：US20120313693A1
公开(公告)日：2012-12-13
申请号：US13491110
申请日：2012-06-07
申请人： Kyung Tae Do , Hyung Ock Kim , Hyo Sig Won , Jung Yun Choi
发明人： Kyung Tae Do , Hyung Ock Kim , Hyo Sig Won , Jung Yun Choi
IPC分类号： G05F3/02
CPC分类号： G06F1/26 , G06F1/04 , G06F1/32
摘要： A method of controlling the provision of a body bias voltage to a logic gate region of a semiconductor device includes; gating application of a clock signal applied to a synchronization element in the logic gate region in accordance with an enable signal, and providing the body bias voltage to each body terminal of a plurality of logic gates arranged in the logic gate region in accordance with the enable signal.
摘要翻译：控制向半导体器件的逻辑栅极区域提供体偏置电压的方法包括：根据使能信号门控施加到逻辑门区域中的同步元件的时钟信号，并根据该使能信号向布置在逻辑门区域中的多个逻辑门极的每个主体端子提供体偏置电压信号。

5. 发明授权

US08156460B2 Method of estimating a leakage current in a semiconductor device 有权
标题翻译：估计半导体器件中漏电流的方法
公开(公告)号：US08156460B2
公开(公告)日：2012-04-10
申请号：US12547729
申请日：2009-08-26
申请人： Kyung-Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
发明人： Kyung-Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.
摘要翻译：在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。通过算术运算实际泄漏特性函数产生单元的虚拟单元泄漏特性函数。通过对片段中所有单元的虚拟单元泄漏特性函数进行算术运算，产生段的段泄漏特性函数。然后，通过统计操作芯片中所有段的段泄漏特性函数来产生芯片的全芯片泄漏特性功能。因此，Wilkinson用于产生全芯片泄漏特性功能的方法的计算负载可以显着降低。

6. 发明申请

US20100058258A1 Method of Estimating a Leakage Current in a Semiconductor Device 有权
标题翻译：估算半导体器件中泄漏电流的方法
公开(公告)号：US20100058258A1
公开(公告)日：2010-03-04
申请号：US12547729
申请日：2009-08-26
申请人： Kyung Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
发明人： Kyung Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.
摘要翻译：在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。通过算术运算实际漏电特性函数产生单元的虚拟单元泄漏特性函数。通过对片段中每个单元的虚拟单元泄漏特性函数进行算术运算来产生段泄漏特性函数。然后，通过统计操作芯片中每个段的段泄漏特性函数来产生全片泄漏特性函数。因此，威尔金森的用于产生全芯片泄漏特性函数的方法的计算量可以显着降低。

7. 发明授权

US07984404B2 Black box timing modeling method and computer system for latch-based subsystem 有权
标题翻译：黑盒定时建模方法和基于闩锁的子系统的计算机系统
公开(公告)号：US07984404B2
公开(公告)日：2011-07-19
申请号：US11934252
申请日：2007-11-02
申请人： Kyung Tae Do , Young Hwan Kim , Haeng Seon Son
发明人： Kyung Tae Do , Young Hwan Kim , Haeng Seon Son
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input connected to the synchronous element and forming the setup time arc using the extracted setup time; and characterizing a clock-to-output delay arc by providing information on an output departure time from an output based on a rising or falling edge of a clock of a closest synchronous element connected to the output, at least partially based on the setup time arc and forming the clock-to-output delay arc. Accordingly, the method can be efficiently used for a latch-based design without re-verifying internal components of the latch-based design during an upper-level verification, thereby reducing verification time and model size.
摘要翻译：提供了一种用于数字电路的黑盒定时建模方法，包括具有锁存器的同步元件。该方法包括：通过相对于连接到同步元件的输入提取相对于同步元件的时钟的上升沿或下降沿的建立时间来表征建立时间弧，并使用所提取的建立时间来形成建立时间弧 ; 以及通过基于建立时间弧至少部分地基于连接到输出的最近同步元件的时钟的上升沿或下降沿从输出提供关于输出离开时间的信息来表征时钟到输出延迟弧并形成时钟到输出的延迟电弧。因此，该方法可以有效地用于基于锁存器的设计，而不会在上级验证期间重新验证基于锁存器的设计的内部部件，从而减少验证时间和型号尺寸。

8. 发明申请

US20120297349A1 METHOD OF DESIGNING A SEMICONDUCTOR DEVICE 失效
标题翻译：设计半导体器件的方法
公开(公告)号：US20120297349A1
公开(公告)日：2012-11-22
申请号：US13458516
申请日：2012-04-27
申请人： Kyung-Tae Do , Yong-Seok Lee , Hyo-Sig Won , Jung-Yun Choi , Jong-Ho Kim
发明人： Kyung-Tae Do , Yong-Seok Lee , Hyo-Sig Won , Jung-Yun Choi , Jong-Ho Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.
摘要翻译：在设计半导体器件的方法中，可以选择包括在半导体器件的布局中的晶体管。可以设置偏置数据以改变所选择的晶体管的特性。可以在忽略偏置数据之后执行用于半导体器件的布局的设计规则检查（DRC）处理。可以基于偏置数据执行用于半导体器件的布局的光学邻近校正（OPC）处理。

9. 发明申请

US20090237107A1 Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same 有权
标题翻译：具有有源时钟屏蔽结构的电路和包括其的半导体集成电路
公开(公告)号：US20090237107A1
公开(公告)日：2009-09-24
申请号：US12381431
申请日：2009-03-12
申请人： Bong-Hyun Lee , Jung-Yun Choi , Jae-Han Jeon , Kyung-Tae Do
发明人： Bong-Hyun Lee , Jung-Yun Choi , Jae-Han Jeon , Kyung-Tae Do
IPC分类号： H03K19/003 , H04B15/00
CPC分类号： H04B15/02 , H04B2215/064
摘要： A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.
摘要翻译：具有有源时钟屏蔽结构的电路包括接收时钟信号并基于时钟信号执行逻辑运算的逻辑电路，基于时钟信号切换逻辑电路的模式的功率门控电路，基于电源门控信号，将时钟信号发送到逻辑电路的时钟信号传输线，以及至少一个电源门控信号传输线，其将电源门控信号发送到电源门控电路并用作与时钟的屏蔽线对信号传输线。

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