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1. 发明申请

US20130086536A1 METHOD OF GENERATING STANDARD CELL LIBRARY FOR DPL PROCESS AND METHODS OF PRODUCING A DPL MASK AND CIRCUIT PATTERN USING THE SAME 审中-公开
标题翻译：用于DPL处理的标准单元库的生成方法和使用该DPL掩模的DPL掩蔽和电路图案的方法
公开(公告)号：US20130086536A1
公开(公告)日：2013-04-04
申请号：US13616507
申请日：2012-09-14
申请人： WOOK KIM , HYUNG OCK KIM , JUNG YUN CHOI , KEE SUP KIM , HYO SIG WON
发明人： WOOK KIM , HYUNG OCK KIM , JUNG YUN CHOI , KEE SUP KIM , HYO SIG WON
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of constructing a standard cell library for double patterning lithography (DPL) includes dividing a standard cell into a first region determined not to have an interaction with an adjacent outer cell and a second region that is likely to have such an interaction, generating data representative of DPL patterns corresponding to the first and second regions, and generating a standard cell library made up of the data. The library is then accessed and used to form a DPL mask. The DPL mask can be used to form a pattern on a substrate made up of a layout of cells in which the pattern of the standard cell is duplicated at several locations in the layout.
摘要翻译：构建用于双重图案化光刻（DPL）的标准单元库的方法包括将标准单元划分成确定为不与相邻外单元相互作用的第一区域和可能具有这种相互作用的第二区域，生成数据代表对应于第一和第二区域的DPL模式，以及生成由数据组成的标准单元库。然后，库被访问并用于形成DPL掩码。 DPL掩模可用于在由其中在布局中的多个位置处复制标准单元的图案的单元布局构成的基板上形成图案。

2. 发明申请

US20070291606A1 SELECTIVE PERFORMANCE OF OPTIMUM POWER CONTROL PROCESS 审中-公开
标题翻译：最佳功率控制过程的选择性能
公开(公告)号：US20070291606A1
公开(公告)日：2007-12-20
申请号：US11670634
申请日：2007-02-02
申请人： Jung Yun CHOI
发明人： Jung Yun CHOI
IPC分类号： G11B7/00
CPC分类号： G11B7/1267 , G11B7/0045
摘要： A power control process in which an inner region optimum power control (“OPC”) value of an inner region of an optical disc is measured at a base speed is selectively performed. A predicted outer region OPC value is calculated based upon the inner region OPC value, a reference laser power associated with the base speed and a desired maximum speed. The predicted outer region OPC value is compared with a laser power limit, and whether to measure an outer region OPC value on an outer region of the optical disc at a desired maximum speed is determined.
摘要翻译：选择性地执行其中以基本速度测量光盘的内部区域的内部区域最佳功率控制（“OPC”）值的功率控制处理。基于内部区域OPC值，与基准速度相关联的参考激光功率和期望的最大速度来计算预测的外部区域OPC值。将预测的外部区域OPC值与激光功率限制进行比较，并且确定是否以期望的最大速度测量光盘的外部区域上的外部区域OPC值。

3. 发明授权

US08621399B2 Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices 失效
标题翻译：设计半导体器件的方法和修改半导体器件布局的方法
公开(公告)号：US08621399B2
公开(公告)日：2013-12-31
申请号：US13458516
申请日：2012-04-27
申请人： Kyung-Tae Do , Yong-Seok Lee , Hyo-Sig Won , Jung-Yun Choi , Jong-Ho Kim
发明人： Kyung-Tae Do , Yong-Seok Lee , Hyo-Sig Won , Jung-Yun Choi , Jong-Ho Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.
摘要翻译：在设计半导体器件的方法中，可以选择包括在半导体器件的布局中的晶体管。可以设置偏置数据以改变所选择的晶体管的特性。可以在忽略偏置数据之后执行用于半导体器件的布局的设计规则检查（DRC）处理。可以基于偏置数据执行用于半导体器件的布局的光学邻近校正（OPC）处理。

4. 发明申请

US20130069690A1 POWER CONTROL CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：功率控制电路，包括其的半导体器件
公开(公告)号：US20130069690A1
公开(公告)日：2013-03-21
申请号：US13603878
申请日：2012-09-05
申请人： Hyung Ock KIM , Jae Han JEON , Jung Yun CHOI , Hyo Sig WON , Kyu Myung CHOI
发明人： Hyung Ock KIM , Jae Han JEON , Jung Yun CHOI , Hyo Sig WON , Kyu Myung CHOI
IPC分类号： H03K17/16
CPC分类号： H03K19/0016 , H03K19/00361 , Y10T307/461 , Y10T307/951
摘要： A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.
摘要翻译：功率控制电路连接在电源电压和逻辑电路之间，以切换提供给逻辑电路的电力。功率控制电路包括并联接收外部模式改变信号的多个第一功率门控单元（PGC），与一个第一PGC连接的至少一个第二PGC，与至少一个第二PGC连接的至少一个第三PGC，以及与所述至少一个第三PGC连接的至少一个第四PGC。第二电源门控单元，第三PGC和/或第四PGC可以包括多个门控单元。第二，第三和第四多个中的至少一个具有串联连接的电力门控单元。第一至第四PGC中的每一个响应于模式改变信号而切换供电。

5. 发明申请

US20120313693A1 SEMICONDUCTOR DEVICE, METHOD AND SYSTEM WITH LOGIC GATE REGION RECEIVING CLOCK SIGNAL AND BODY BIAS VOLTAGE BY ENABLE SIGNAL 审中-公开
标题翻译：半导体器件，具有逻辑门控区域的接收时钟信号的方法和系统和通过使能信号进行的体虚电压
公开(公告)号：US20120313693A1
公开(公告)日：2012-12-13
申请号：US13491110
申请日：2012-06-07
申请人： Kyung Tae Do , Hyung Ock Kim , Hyo Sig Won , Jung Yun Choi
发明人： Kyung Tae Do , Hyung Ock Kim , Hyo Sig Won , Jung Yun Choi
IPC分类号： G05F3/02
CPC分类号： G06F1/26 , G06F1/04 , G06F1/32
摘要： A method of controlling the provision of a body bias voltage to a logic gate region of a semiconductor device includes; gating application of a clock signal applied to a synchronization element in the logic gate region in accordance with an enable signal, and providing the body bias voltage to each body terminal of a plurality of logic gates arranged in the logic gate region in accordance with the enable signal.
摘要翻译：控制向半导体器件的逻辑栅极区域提供体偏置电压的方法包括：根据使能信号门控施加到逻辑门区域中的同步元件的时钟信号，并根据该使能信号向布置在逻辑门区域中的多个逻辑门极的每个主体端子提供体偏置电压信号。

6. 发明授权

US08156460B2 Method of estimating a leakage current in a semiconductor device 有权
标题翻译：估计半导体器件中漏电流的方法
公开(公告)号：US08156460B2
公开(公告)日：2012-04-10
申请号：US12547729
申请日：2009-08-26
申请人： Kyung-Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
发明人： Kyung-Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.
摘要翻译：在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。通过算术运算实际泄漏特性函数产生单元的虚拟单元泄漏特性函数。通过对片段中所有单元的虚拟单元泄漏特性函数进行算术运算，产生段的段泄漏特性函数。然后，通过统计操作芯片中所有段的段泄漏特性函数来产生芯片的全芯片泄漏特性功能。因此，Wilkinson用于产生全芯片泄漏特性功能的方法的计算负载可以显着降低。

7. 发明授权

US07948263B2 Power gating circuit and integrated circuit including same 有权
标题翻译：电源门控电路和集成电路包括相同
公开(公告)号：US07948263B2
公开(公告)日：2011-05-24
申请号：US12719472
申请日：2010-03-08
申请人： Hyung-Ock Kim , Jung-Yun Choi , Bong-Hyun Lee , Mun-Jun Seo , Youngsoo Shin
发明人： Hyung-Ock Kim , Jung-Yun Choi , Bong-Hyun Lee , Mun-Jun Seo , Youngsoo Shin
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0016 , H03K19/0013
摘要： A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.
摘要翻译：电源门控电路包括逻辑电路，开关元件和保持触发器。逻辑电路耦合在第一电源轨和虚拟电源轨之间。响应于指示活动模式或待机模式的模式控制信号，开关元件将虚拟电源轨选择性地耦合到第二电源轨。保持触发器响应于虚拟电源轨的电压选择性地执行触发器操作或数据保持操作。

8. 发明申请

US20100231255A1 Power Gating Circuit and Integrated Circuit Including Same 有权
标题翻译：电源门控电路和集成电路包括相同
公开(公告)号：US20100231255A1
公开(公告)日：2010-09-16
申请号：US12719472
申请日：2010-03-08
申请人： Hyung-Ock Kim , Jung-Yun Choi , Bong-Hyun Lee , Jun Seomun , Youngsoo Shin
发明人： Hyung-Ock Kim , Jung-Yun Choi , Bong-Hyun Lee , Jun Seomun , Youngsoo Shin
IPC分类号： H03K19/003
CPC分类号： H03K19/0016 , H03K19/0013
摘要： A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.
摘要翻译：电源门控电路包括逻辑电路，开关元件和保持触发器。逻辑电路耦合在第一电源轨和虚拟电源轨之间。响应于指示活动模式或待机模式的模式控制信号，开关元件将虚拟电源轨选择性地耦合到第二电源轨。保持触发器响应于虚拟电源轨的电压选择性地执行触发器操作或数据保持操作。

9. 发明申请

US20100058258A1 Method of Estimating a Leakage Current in a Semiconductor Device 有权
标题翻译：估算半导体器件中泄漏电流的方法
公开(公告)号：US20100058258A1
公开(公告)日：2010-03-04
申请号：US12547729
申请日：2009-08-26
申请人： Kyung Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
发明人： Kyung Tae Do , Jung-Yun Choi , Bong-Hyun Lee , Young-Hwan Kim , Hyo-Sig Won , Wook Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.
摘要翻译：在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。通过算术运算实际漏电特性函数产生单元的虚拟单元泄漏特性函数。通过对片段中每个单元的虚拟单元泄漏特性函数进行算术运算来产生段泄漏特性函数。然后，通过统计操作芯片中每个段的段泄漏特性函数来产生全片泄漏特性函数。因此，威尔金森的用于产生全芯片泄漏特性函数的方法的计算量可以显着降低。

10. 发明授权

US07616048B2 Body biasing control circuit using lookup table and body biasing control method using same 有权
标题翻译：使用查找表和身体偏置控制方法使用本体偏置控制电路
公开(公告)号：US07616048B2
公开(公告)日：2009-11-10
申请号：US11849486
申请日：2007-09-04
申请人： Byunghee Choi , Jun Seomun , Jung-yun Choi , Hyo-sig Won , Youngsoo Shin
发明人： Byunghee Choi , Jun Seomun , Jung-yun Choi , Hyo-sig Won , Youngsoo Shin
IPC分类号： H03K3/01
CPC分类号： H03K19/00384 , G05F3/205 , H03K2217/0018
摘要： A body biasing control circuit capable of being shared by a plurality of macro blocks and can independently control body voltages of a plurality of macro blocks. The body biasing control circuit includes a lookup table for storing a plurality of indexes where each index is associated with a body voltage appropriate for an operating state of a corresponding macro block. A control unit receives a corresponding index from the lookup table and generates a plurality of body voltages appropriate for an operating state of a macro block corresponding to the index and supplies the body voltages to the macro block.
摘要翻译：一种能够被多个宏块共享的主体偏置控制电路，并且可以独立地控制多个宏块的体电压。身体偏置控制电路包括用于存储多个索引的查找表，其中每个索引与适于相应的宏块的操作状态的体电压相关联。控制单元从查找表接收相应的索引，并产生适合于与索引相对应的宏块的操作状态的多个体电压，并将体电压提供给宏块。

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