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1. 发明授权

US06693985B2 Clock and data recovery method and apparatus 有权
标题翻译：时钟和数据恢复方法和装置
公开(公告)号：US06693985B2
公开(公告)日：2004-02-17
申请号：US10043886
申请日：2001-10-26
申请人： Hung Sung Li , Ook Kim
发明人： Hung Sung Li , Ook Kim
IPC分类号： H04L700
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/087 , H04L7/0337
摘要： Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal. The determination is based, in one embodiment, on the order and value of the samples taken, which indicate whether the samples are taken too close to a transition of the received signal.
摘要翻译：时钟和数据恢复方法和装置的实施例包括接收多通道串行数字编码信号并将接收的信号转换为数字数据或二进制字符的集合。一个实施例包括确定采样电路的相位是否适合于从接收信号中采样有意义的数据; 如果采样电路的相位不合适，则相位被移位，使得针对接收信号更早或更晚地进行采样。在一个实施例中，该确定基于所采集的样本的顺序和值，其指示采样是否太接近于接收到的信号的转变。

2. 发明授权

US06809567B1 System and method for multiple-phase clock generation 有权
标题翻译：用于多相时钟生成的系统和方法
公开(公告)号：US06809567B1
公开(公告)日：2004-10-26
申请号：US09989645
申请日：2001-11-20
申请人： Ook Kim , Hung Sung Li , Inyeol Lee , Gyudong Kim , Yongman Lee
发明人： Ook Kim , Hung Sung Li , Inyeol Lee , Gyudong Kim , Yongman Lee
IPC分类号： H03L700
CPC分类号： H03K23/542 , G06F1/06 , H03K5/15013 , H03L7/0891 , H03L7/0995
摘要： A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.
摘要翻译：公开了一种用于多相时钟产生的系统和方法。在一个实施例中，多级压控振荡器（“VCO”）将多个时钟相位发送到产生期望数量的时钟相位输出的时钟分频器电路。该实施例中的时钟分频器电路包括一个状态机，例如修改的约翰逊计数器，其提供多个划分的下降时钟相位，每个分频下降沿连接到单独的修改的移位寄存器。每个修改的移位寄存器包含D型触发器，每个D型触发器提供单独的时钟相位输出。在一个实施例中，多相时钟的时钟相位输出的数量是VCO时钟相位数乘以修改的约翰逊计数器中期望状态数量的函数。

3. 发明授权

US06717478B1 Multi-phase voltage controlled oscillator (VCO) with common mode control 有权
标题翻译：具有共模控制的多相压控振荡器（VCO）
公开(公告)号：US06717478B1
公开(公告)日：2004-04-06
申请号：US09989587
申请日：2001-11-20
申请人： Ook Kim , Hung Sung Li , Inyeol Lee , Gyudong Kim , Yongman Lee
发明人： Ook Kim , Hung Sung Li , Inyeol Lee , Gyudong Kim , Yongman Lee
IPC分类号： H03B2700
CPC分类号： H03L7/0995 , H03B5/24 , H03B27/00 , H03L7/0891
摘要： A voltage controlled oscillator (“VCO”) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.
摘要翻译：提供了能够产生具有降低的抖动和/或低相位噪声的信号的压控振荡器（“VCO”）电路。一个实施例提供多个级联VCO单元，其中每个VCO单元可以包括源极耦合差分对，连接到差分对的偏置晶体管，用于偏置差分对，连接到差分对的电阻负载对，以及电压控制电容器对或变容二极管对连接到差分对。变容二极管提供对由VCO电路产生的振荡频率与控制电压的组合的控制。与电荷泵和环路滤波器组合的相位检波器提供控制电压。

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