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    • 1. 发明授权
    • Clock and data recovery method and apparatus
    • 时钟和数据恢复方法和装置
    • US06693985B2
    • 2004-02-17
    • US10043886
    • 2001-10-26
    • Hung Sung LiOok Kim
    • Hung Sung LiOok Kim
    • H04L700
    • H03L7/091H03L7/0814H03L7/087H04L7/0337
    • Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal. The determination is based, in one embodiment, on the order and value of the samples taken, which indicate whether the samples are taken too close to a transition of the received signal.
    • 时钟和数据恢复方法和装置的实施例包括接收多通道串行数字编码信号并将接收的信号转换为数字数据或二进制字符的集合。 一个实施例包括确定采样电路的相位是否适合于从接收信号中采样有意义的数据; 如果采样电路的相位不合适,则相位被移位,使得针对接收信号更早或更晚地进行采样。 在一个实施例中,该确定基于所采集的样本的顺序和值,其指示采样是否太接近于接收到的信号的转变。
    • 2. 发明授权
    • System and method for multiple-phase clock generation
    • 用于多相时钟生成的系统和方法
    • US06809567B1
    • 2004-10-26
    • US09989645
    • 2001-11-20
    • Ook KimHung Sung LiInyeol LeeGyudong KimYongman Lee
    • Ook KimHung Sung LiInyeol LeeGyudong KimYongman Lee
    • H03L700
    • H03K23/542G06F1/06H03K5/15013H03L7/0891H03L7/0995
    • A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.
    • 公开了一种用于多相时钟产生的系统和方法。 在一个实施例中,多级压控振荡器(“VCO”)将多个时钟相位发送到产生期望数量的时钟相位输出的时钟分频器电路。 该实施例中的时钟分频器电路包括一个状态机,例如修改的约翰逊计数器,其提供多个划分的下降时钟相位,每个分频下降沿连接到单独的修改的移位寄存器。 每个修改的移位寄存器包含D型触发器,每个D型触发器提供单独的时钟相位输出。 在一个实施例中,多相时钟的时钟相位输出的数量是VCO时钟相位数乘以修改的约翰逊计数器中期望状态数量的函数。
    • 4. 发明授权
    • Cable with circuitry for asserting stored cable data or other information to an external device or user
    • 电缆,用于断开存储的电缆数据或其他信息到外部设备或用户的电路
    • US07500032B2
    • 2009-03-03
    • US11848758
    • 2007-08-31
    • Ook KimEric LeeGyudong KimZeehoon JangBaegin SungNam Hoon KimGijung AhnSeung Ho Hwang
    • Ook KimEric LeeGyudong KimZeehoon JangBaegin SungNam Hoon KimGijung AhnSeung Ho Hwang
    • G06F13/38
    • G06F13/385
    • A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
    • 包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。 电缆可以包括导体,存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路,并且将所访问的数据串行地认定到至少一个导体 (例如,用于传输到外部设备)。 本发明的其他方面是用于访问存储在电缆中并且可选地使用数据(例如,实现均衡)的电缆数据的方法。 电缆数据可以表示电缆类型,等级,速度,长度和阻抗的全部或一些,日期代码,频率相关衰减表,远端串扰和EMI相关系数,共模辐射,内部对 歪斜等信息。 电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色,亮度和/或闪烁图案的驱动信号的电路。
    • 5. 发明申请
    • Cable with Circuitry for Asserting Stored Cable Data or Other Information to an External Device or User
    • 电缆用于将存储的电缆数据或其他信息提供给外部设备或用户
    • US20080022023A1
    • 2008-01-24
    • US11848758
    • 2007-08-31
    • Ook KimEric LeeGyudong KimZeehoon JangBaegin SungNam KimGijung AhnSeung Hwang
    • Ook KimEric LeeGyudong KimZeehoon JangBaegin SungNam KimGijung AhnSeung Hwang
    • G06F13/38G06F3/00
    • G06F13/385
    • A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
    • 包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。 电缆可以包括导体,存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路,并且将所访问的数据串行地认定到至少一个导体 (例如,用于传输到外部设备)。 本发明的其他方面是用于访问存储在电缆中并且可选地使用数据(例如,实现均衡)的电缆数据的方法。 电缆数据可以表示电缆类型,等级,速度,长度和阻抗的全部或一些,日期代码,频率相关衰减表,远端串扰和EMI相关系数,共模辐射,内部对 歪斜等信息。 电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色,亮度和/或闪烁图案的驱动信号的电路。
    • 7. 发明授权
    • Method and circuit for adaptive equalization of multiple signals in response to a control signal generated from one of the equalized signals
    • 响应于从一个均衡信号产生的控制信号,多个信号的自适应均衡的方法和电路
    • US07502411B2
    • 2009-03-10
    • US10794015
    • 2004-03-05
    • Ook KimGyudong Kim
    • Ook KimGyudong Kim
    • H03H7/30H03H7/40
    • H04L25/03019
    • In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal. In other embodiments, the invention is an adaptive equalization circuit including an equalization filter and circuitry for generating a control signal for the filter in response to a signal indicative of a predetermined fixed pattern, a receiver including an adaptive equalization circuit, a system including such a receiver, and a method for adaptive equalization of signals received over a multi-channel serial link.
    • 在优选实施例中,自适应均衡电路包括至少两个均衡滤波器(每个用于均衡通过多通道串行链路传输的信号)和用于产生用于所有滤波器的均衡控制信号的控制电路。 控制电路响应于由滤波器之一产生的均衡信号而产生控制信号,并将控制信号置为全部滤波器。 优选地,一个滤波器响应于固定模式信号(例如,时钟信号)产生均衡的固定模式信号,每个其他滤波器均衡数据信号,并且控制电路响应于均衡的固定模式信号而产生控制信号。 在其他实施例中,本发明是一种自适应均衡电路,包括均衡滤波器和用于响应于指示预定固定模式的信号产生用于滤波器的控制信号的电路,包括自适应均衡电路的接收机, 接收机和用于通过多声道串行链路接收的信号的自适应均衡的方法。
    • 8. 发明申请
    • Cable with circuitry for asserting stored cable data or other information to an external device or user
    • 电缆,用于将存储的电缆数据或其他信息断言给外部设备或用户
    • US20050182876A1
    • 2005-08-18
    • US10781405
    • 2004-02-18
    • Ook KimEric LeeGyudong KimZeehoon JangBaegin SungNam KimGijung AhnSeung Hwang
    • Ook KimEric LeeGyudong KimZeehoon JangBaegin SungNam KimGijung AhnSeung Hwang
    • G06F13/00G06F13/38
    • G06F13/385
    • A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
    • 包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。 电缆可以包括导体,存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路,并且将所访问的数据串行地认定到至少一个导体 (例如,用于传输到外部设备)。 本发明的其他方面是用于访问存储在电缆中并且可选地使用数据(例如,实现均衡)的电缆数据的方法。 电缆数据可以表示电缆类型,等级,速度,长度和阻抗的全部或一些,日期代码,频率相关衰减表,远端串扰和EMI相关系数,共模辐射,内部对 歪斜等信息。 电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色,亮度和/或闪烁图案的驱动信号的电路。
    • 9. 发明授权
    • High-speed bus with embedded clock signals
    • 具有嵌入式时钟信号的高速总线
    • US06845461B1
    • 2005-01-18
    • US09989590
    • 2001-11-20
    • Ook Kim
    • Ook Kim
    • G06F13/14G06F13/42
    • G06F13/4278
    • A system and method for embedding at least one clock signal into bus lines that also carry data signals at other times to enable a high-speed bus is disclosed. Each bus line is used for carrying both clock and data information at different times. Data signals, which may be either encoded or not, are carried through a subset of the bus lines through a mapping scheme that maps the data information to the bus lines at each data transfer while the clock signals are carried in the remaining bus lines. Various mapping schemes are possible.
    • 公开了一种用于将至少一个时钟信号嵌入总线的系统和方法,该总线还在其它时间承载数据信号,以实现高速总线。 每条总线用于在不同时间承载时钟和数据信息。 数据信号可以是编码的,也可以是编码的,通过映射方案,通过映射方案,将数据信息映射到总线,同时在剩余的总线中携带时钟信号。 各种映射方案是可能的。