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1. 发明授权

US08293460B2 Double exposure patterning with carbonaceous hardmask 失效
标题翻译：用碳质硬掩模进行双重曝光图案化
公开(公告)号：US08293460B2
公开(公告)日：2012-10-23
申请号：US12339836
申请日：2008-12-19
申请人： Hui W. Chen , Chorng-Ping Chang , Yongmei Chen , Huixiong Dai , Jiahua Yu , Susie X. Yang , Xumou Xu , Christopher D. Bencher , Raymond Hoiman Hung , Michael P. Duane , Christopher Siu Wing Ngai , Jen Shu , Kenneth MacWilliams
发明人： Hui W. Chen , Chorng-Ping Chang , Yongmei Chen , Huixiong Dai , Jiahua Yu , Susie X. Yang , Xumou Xu , Christopher D. Bencher , Raymond Hoiman Hung , Michael P. Duane , Christopher Siu Wing Ngai , Jen Shu , Kenneth MacWilliams
IPC分类号： G03F7/20
CPC分类号： G03F7/11 , G03F7/091 , G03F7/2022
摘要： Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.
摘要翻译：通过不止一次地曝光光致抗蚀剂层来对衬底层中的特征进行图案化的方法。在一个实施例中，单个掩模版可以在连续曝光之间实现的覆盖偏移曝光不止一次以减小掩模版的半间距。在特定实施例中，可以使用这些方法来减少用65nm生成光刻设备印刷的特征的半间距，以实现45nm光刻产生CD和间距性能。

2. 发明授权

US06469390B2 Device comprising thermally stable, low dielectric constant material 有权
标题翻译：装置包括热稳定的低介电常数材料
公开(公告)号：US06469390B2
公开(公告)日：2002-10-22
申请号：US09296001
申请日：1999-04-21
申请人： Chorng-Ping Chang , Kin Ping Cheung , Chien-Shing Pai , Wei Zhu
发明人： Chorng-Ping Chang , Kin Ping Cheung , Chien-Shing Pai , Wei Zhu
IPC分类号： H01L2348
CPC分类号： H01L23/5222 , H01L23/5329 , H01L2924/0002 , Y10S977/70 , H01L2924/00
摘要： It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.
摘要翻译：已经发现，对于诸如MOSFET的半导体器件，在前端结构中存在显着的电容耦合，即从器件衬底到第一金属互连级别的结构。因此，本发明提供了一种包括硅衬底，衬底中的隔离结构（例如，浅沟槽隔离），有源器件结构（例如，晶体管结构），有源器件结构上的介电层以及金属互连层（介电层）（金属-1层）。前端结构的介电部件中的至少一个包括介电常数小于3.5的材料。这种相对低的介电常数材料减少了前端结构中的电容耦合，从而在器件中提供了改进的特性。

3. 发明申请

US20090189201A1 INWARD DIELECTRIC SPACERS FOR REPLACEMENT GATE INTEGRATION SCHEME 审中-公开
标题翻译：用于替换门控集成方案的电介质间隔器
公开(公告)号：US20090189201A1
公开(公告)日：2009-07-30
申请号：US12019538
申请日：2008-01-24
申请人： Chorng-Ping Chang , Bingxi Sun Wood
发明人： Chorng-Ping Chang , Bingxi Sun Wood
IPC分类号： H01L21/44 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： Inward dielectric spacers for a replacement gate integration scheme are described. A semiconductor device is fabricated by first providing a substrate having thereon a placeholder gate electrode disposed in a dielectric layer. The placeholder gate electrode is removed to from a trench in the dielectric layer. A pair of dielectric spacers is then formed adjacent to the sidewalls of the trench. Finally, a gate electrode is formed in the trench and adjacent to the pair of dielectric layers.
摘要翻译：描述用于替代栅极集成方案的内置电介质间隔物。通过首先提供其上设置有介电层中的占位符栅电极的衬底来制造半导体器件。占位符栅电极从电介质层中的沟槽去除。然后在沟槽的侧壁附近形成一对电介质间隔物。最后，在沟槽中形成栅电极并与该对电介质层相邻。

4. 发明申请

US20090179285A1 METAL GATE ELECTRODES FOR REPLACEMENT GATE INTEGRATION SCHEME 有权
标题翻译：用于替代浇注整合方案的金属门电极
公开(公告)号：US20090179285A1
公开(公告)日：2009-07-16
申请号：US11972439
申请日：2008-01-10
申请人： Bingxi Sun Wood , Chorng-Ping Chang
发明人： Bingxi Sun Wood , Chorng-Ping Chang
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L21/28088 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of the trench and above the substrate. A gate electrode has a work-function-setting layer disposed along the sidewalls of the trench and above the gate dielectric layer at the bottom of the trench. The work-function-setting layer has a thickness at the bottom of the trench greater than the thickness along the sidewalls of the trench. A pair of source and drain regions is disposed in the substrate, on either side of the gate electrode.
摘要翻译：描述了用于替换栅极集成方案的金属栅电极。半导体器件包括其上设置有电介质层的衬底。沟槽设置在电介质层中。栅极电介质层设置在沟槽的底部和衬底上方。栅电极具有沿着沟槽的侧壁设置并在沟槽底部的栅介质层上方设置的功函设定层。工作功能设定层的厚度在沟槽底部的厚度大于沟槽侧壁的厚度。一对源极和漏极区域设置在栅极电极的任一侧上的衬底中。

5. 发明申请

US20080026584A1 LPCVD gate hard mask 失效
标题翻译： LPCVD门硬掩模
公开(公告)号：US20080026584A1
公开(公告)日：2008-01-31
申请号：US11492316
申请日：2006-07-25
申请人： Rajesh Kanuri , Chorng-Ping Chang , Christopher Dennis Bencher , Hoiman Hung
发明人： Rajesh Kanuri , Chorng-Ping Chang , Christopher Dennis Bencher , Hoiman Hung
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/02123 , H01L21/02271 , H01L21/02337 , H01L21/31612
摘要： A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.
摘要翻译：使用低压化学气相沉积（LPCVD）将栅极硬掩模沉积在栅极结构上。通过这样做，与现有技术的硬掩模相比，栅极硬掩模相对于下面的多晶硅栅极层的湿蚀刻去除率（WERR）增加。 LPCVD栅极硬掩模将不仅比现有技术的硬掩模蚀刻更快，而且还将减少栅极氧化物的底切。为了提供对湿蚀刻速率的额外控制，LPCVD硬掩模可被退火。可以定制退火以实现所需的蚀刻速率。

6. 发明申请

US20130320542A1 Method of fabricating a self-aligned buried bit line for a vertical channel dram 有权
标题翻译：制造垂直通道的自对准埋置位线的方法
公开(公告)号：US20130320542A1
公开(公告)日：2013-12-05
申请号：US13986499
申请日：2013-05-08
申请人： Chorng-Ping Chang , Bingxi Wood , Er-Xuan Ping
发明人： Chorng-Ping Chang , Bingxi Wood , Er-Xuan Ping
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L21/76889 , H01L21/743 , H01L23/498 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less.
摘要翻译：在构成垂直通道DRAM的一部分的结构中制造自对准埋入位线的方法。所使用的材料和工艺在制造过程中能够对掩埋位线的元件进行自对准。此外，所使用的材料和工艺能够形成具有16nm或更小的掩埋位线宽度的各个DRAM单元。

7. 发明授权

US07892911B2 Metal gate electrodes for replacement gate integration scheme 有权
标题翻译：用于替代栅极集成方案的金属栅电极
公开(公告)号：US07892911B2
公开(公告)日：2011-02-22
申请号：US11972439
申请日：2008-01-10
申请人： Bingxi Sun Wood , Chorng-Ping Chang
发明人： Bingxi Sun Wood , Chorng-Ping Chang
IPC分类号： H01L21/8238
CPC分类号： H01L21/28088 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of the trench and above the substrate. A gate electrode has a work-function-setting layer disposed along the sidewalls of the trench and above the gate dielectric layer at the bottom of the trench. The work-function-setting layer has a thickness at the bottom of the trench greater than the thickness along the sidewalls of the trench. A pair of source and drain regions is disposed in the substrate, on either side of the gate electrode.
摘要翻译：描述了用于替换栅极集成方案的金属栅电极。半导体器件包括其上设置有电介质层的衬底。沟槽设置在电介质层中。栅极电介质层设置在沟槽的底部和衬底上方。栅电极具有沿着沟槽的侧壁设置并在沟槽底部的栅介质层上方设置的功函设定层。工作功能设定层的厚度在沟槽底部的厚度大于沟槽侧壁的厚度。一对源极和漏极区域设置在栅极电极的任一侧上的衬底中。

8. 发明授权

US5438006A Method of fabricating gate stack having a reduced height 失效
标题翻译：制造具有减小的高度的栅极堆叠的方法
公开(公告)号：US5438006A
公开(公告)日：1995-08-01
申请号：US176600
申请日：1994-01-03
申请人： Chorng-Ping Chang , Kuo-Hua Lee , Chun-Ting Liu , Ruichen Liu
发明人： Chorng-Ping Chang , Kuo-Hua Lee , Chun-Ting Liu , Ruichen Liu
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/088 , H01L21/8232
CPC分类号： H01L21/28123 , Y10S148/105
摘要： An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.
摘要翻译：通过使用图案化的氧化物硬掩模对下面的金属层进行图案来制造具有降低栅极叠层的集成电路器件。去除氧化物掩模，随后使用图案化的金属作为掩模来蚀刻多晶硅层。

9. 发明授权

US07547621B2 LPCVD gate hard mask 失效
标题翻译： LPCVD门硬掩模
公开(公告)号：US07547621B2
公开(公告)日：2009-06-16
申请号：US11492316
申请日：2006-07-25
申请人： Rajesh Kanuri , Chorng-Ping Chang , Christopher Dennis Bencher , Hoiman Hung
发明人： Rajesh Kanuri , Chorng-Ping Chang , Christopher Dennis Bencher , Hoiman Hung
IPC分类号： H01L21/20
CPC分类号： H01L21/32139 , H01L21/02123 , H01L21/02271 , H01L21/02337 , H01L21/31612
摘要： A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.
摘要翻译：使用低压化学气相沉积（LPCVD）将栅极硬掩模沉积在栅极结构上。通过这样做，与现有技术的硬掩模相比，栅极硬掩模相对于下面的多晶硅栅极层的湿蚀刻去除率（WERR）增加。 LPCVD栅极硬掩模将不仅比现有技术的硬掩模蚀刻更快，而且还将减少栅极氧化物的底切。为了提供对湿蚀刻速率的额外控制，LPCVD硬掩模可被退火。可以定制退火以实现所需的蚀刻速率。

10. 发明授权

US06566224B1 Process for device fabrication 失效
标题翻译：器件制造工艺
公开(公告)号：US06566224B1
公开(公告)日：2003-05-20
申请号：US08903974
申请日：1997-07-31
申请人： Chorng-Ping Chang , Chien-Shing Pai
发明人： Chorng-Ping Chang , Chien-Shing Pai
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： The invention is a process for device fabrication that utilizes shallow trench isolation. The process involves the steps of forming an oxidation barrier region, e.g., silicon nitride, above a silicon substrate, providing an opening in the oxidation barrier region and in any underlying regions deposited on the silicon, providing a trench in the silicon substrate at the opening, depositing a dielectric material such as silicon dioxide in the trench, typically planarizing the trench silicon dioxide, and subsequently performing an oxidation step. The oxidation step rounds the otherwise sharp corners of the silicon at the area where the trench silicon dioxide meets the pad oxide. The invention thereby reduces or eliminates sharp corners that contribute to leakage current.
摘要翻译：本发明是利用浅沟槽隔离的器件制造工艺。该方法包括以下步骤：在硅衬底之上形成氧化阻挡区域，例如氮化硅，在氧化阻挡区域和沉积在硅上的任何下层区域提供开口，在开口处的硅衬底中提供沟槽，在沟槽中沉积诸如二氧化硅的电介质材料，通常对沟槽二氧化硅进行平面化，随后执行氧化步骤。在沟槽二氧化硅与衬垫氧化物相遇的区域，氧化步骤回绕硅的其它尖角。因此，本发明减少或消除了有助于泄漏电流的尖角。

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