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1. 发明申请

US20050194592A1 Adaptive voltage control for performance and energy optimization 有权
标题翻译：用于性能和能量优化的自适应电压控制
公开(公告)号：US20050194592A1
公开(公告)日：2005-09-08
申请号：US11045222
申请日：2005-01-28
申请人： Hugh Mair , Gordon Gammie , Alice Wang
发明人： Hugh Mair , Gordon Gammie , Alice Wang
IPC分类号： H01L29/04
CPC分类号： G11C5/147
摘要： A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first tracking element coupled to the processing module and producing a first value indicative of a first estimated speed associated with the circuitry, and a second tracking element coupled to the processing module and producing a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to a target value and causes a voltage output to be adjusted based on said comparison.
摘要翻译：一种用于自适应地控制提供给基本上靠近设备的电路的电压的装置，包括处理模块，耦合到处理模块的第一跟踪元件，并产生指示与电路相关联的第一估计速度的第一值，以及第二跟踪元件耦合到所述处理模块并产生指示与所述电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与目标值进行比较，并且基于所述比较使电压输出被调整。

2. 发明申请

US20080307240A1 POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE 审中-公开
标题翻译：电力管理电子电路，系统及其制造方法和工艺
公开(公告)号：US20080307240A1
公开(公告)日：2008-12-11
申请号：US11760263
申请日：2007-06-08
申请人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
发明人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/06 , G06F1/08 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F21/79 , Y02D10/126 , Y02D10/128 , Y02D10/172 , Y02D50/20
摘要： An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).
摘要翻译：一种电子电路，包括功率管理电路（2610）和耦合到功率管理电路（2610）的功率管理控制电路（3570），并且可操作以在至少第一操作性能点（OPP1）和第二较高操作功率管理电路（2610）的性能点（OPP2），每个性能点包括电压和工作频率的相应对（Vn，Fn），并且功率管理控制电路（3570）还可操作以控制功率管理电路功率管理电路（2610），其中在给定操作性能点处的功率管理电路（2610）具有静态功耗（4820.1），并且动态功率开关将功率管理电路置于较低的静态功率状态 4860.1），功耗比静态功耗（4820.1）要低。

3. 发明授权

US06903780B2 Method of expanding high-speed serial video data providing compatibility with a class of DVI receivers 有权
标题翻译：扩展与一类DVI接收机兼容的高速串行视频数据的方法
公开(公告)号：US06903780B2
公开(公告)日：2005-06-07
申请号：US09966167
申请日：2001-09-28
申请人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
发明人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
IPC分类号： G09G5/00 , H03M7/30 , H04L25/49 , H04N7/24 , H04N7/26 , H04N7/04
CPC分类号： G09G5/006 , H03M7/30 , H04L25/4908 , H04N7/24 , H04N19/184
摘要： A method of expanding data to a high-speed serial video link in such a way that it is invisible to existing receivers and such that auxiliary data, i.e. audio data, can be transmitted without any knowledge of the capabilities of the display to receive the auxiliary data.
摘要翻译：一种将数据扩展到高速串行视频链路的方式，使得现有接收机不可见，并且可以传输辅助数据（即，音频数据），而无需了解显示器的能力来接收辅助信号数据。

4. 发明授权

US06633243B2 Method of encoding video data for serial transmission 有权
标题翻译：编码串行传输的视频数据的方法
公开(公告)号：US06633243B2
公开(公告)日：2003-10-14
申请号：US09953803
申请日：2001-09-17
申请人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
发明人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
IPC分类号： H03M700
CPC分类号： G09G5/006 , H03M7/14 , H04L25/4908 , H04N19/184
摘要： An encoding scheme simplifies the TMDS encoding algorithm described in the DVI 1.0 specification while retaining compatibility with most existing DVI receivers. The generation of the Transition Control bit has been removed; and although the INV bit has a similar function to the DC bit in the DVI 1.0 standard, the algorithm for deriving it is very different. No attempt is made to maintain a DC balance on the cable. Instead, the INV bit is set to a ‘1’ for the purpose of removing ‘rogue’ character sequences; otherwise it is always set to a ‘0’.
摘要翻译：编码方案简化了DVI 1.0规范中描述的TMDS编码算法，同时保留了与大多数现有DVI接收器的兼容性。过渡控制位的生成已被删除; 虽然INV位具有与DVI 1.0标准中的DC位相似的功能，但是用于推导它的算法是非常不同的。不要在电缆上维持直流平衡。相反，为了消除“流氓”字符序列，将INV位设置为“1” 否则始终设置为“0”。

5. 发明授权

US06912008B2 Method of adding data to a data communication link while retaining backward compatibility 有权
标题翻译：将数据添加到数据通信链路同时保留向后兼容性的方法
公开(公告)号：US06912008B2
公开(公告)日：2005-06-28
申请号：US09978823
申请日：2001-10-15
申请人： Hugh Mair , Gordon Gammie
发明人： Hugh Mair , Gordon Gammie
IPC分类号： H04N7/00 , H04N7/025 , H04N7/08 , H04N7/084
CPC分类号： H04N7/025 , H04N7/08
摘要： A method of adding auxiliary data, e.g., audio data, to a high-speed serial video link in such a way that it is invisible to existing receiver and such that auxiliary data, e.g., audio, can be transmitted without any knowledge of the capabilities of the display to receive the auxiliary data. Some of the DC balancing bits are used to transport the auxiliary data information over the link in a manner that does not change the data recovered by a DVI-CE receiver, or a legacy receiver (installed base). DC balancing is also maintained, but with differences over known techniques. Since the auxiliary data bits (which are occupying the time slots of the DC balance bits) will be interpreted by legacy receivers as DC balance bits, the data must be optionally inverted to remain consistent with the value of the auxiliary data bit being transmitted. The DC balance bit that is transmitted at the beginning of each group of four words must also invert the value of the auxiliary data to allow the DC balancing to be achieved independent of the auxiliary data.
摘要翻译：将辅助数据（例如，音频数据）添加到高速串行视频链路的方式，使得它对于现有的接收机是不可见的，并且可以在没有能力的知识的情况下传输诸如音频的辅助数据的显示器接收辅助数据。一些DC平衡位用于以不改变由DVI-CE接收机或遗留接收机（已安装基座）恢复的数据的方式通过链路传输辅助数据信息。 DC平衡也得到保持，但与已知技术的差异。由于辅助数据位（占用直流平衡比特的时隙）将由传统接收机解释为直流平衡比特，所以数据必须可选地反转以保持与被发送的辅助数据比特的值一致。在每组四个字的开始处发送的直流平衡位也必须反转辅助数据的值，以允许独立于辅助数据实现直流平衡。

6. 发明申请

US20100103760A1 Memory Power Management Systems and Methods 有权
标题翻译：内存电源管理系统和方法
公开(公告)号：US20100103760A1
公开(公告)日：2010-04-29
申请号：US12258747
申请日：2008-10-27
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

7. 发明授权

US08302047B2 Statistical static timing analysis in non-linear regions 有权
标题翻译：非线性区域的统计静态时序分析
公开(公告)号：US08302047B2
公开(公告)日：2012-10-30
申请号：US12766643
申请日：2010-04-23
申请人： Dennis Darcy Buss , Alice Wang , Gordon Gammie , Jle Gu , Rahul Jagdish Rithe , Satyendra R. P. Raju Datla , Sharon Hsiao-Wei Chou
发明人： Dennis Darcy Buss , Alice Wang , Gordon Gammie , Jle Gu , Rahul Jagdish Rithe , Satyendra R. P. Raju Datla , Sharon Hsiao-Wei Chou
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： H03G9/025 , G10L19/00 , H03G7/007 , H03G9/00 , H03G9/005
摘要： A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.
摘要翻译：描述了当本地晶体管变化确定随机延迟时模拟集成电路设计的f-sigma定时路径延迟的方法。这通过使用局部变化（NLOPALV）的非线性工作点分析来确定第一定时路径的估计延迟时间来实现。为集成电路设计中的定时路径中包含的每个单元计算工作点。电池弧的f-σ工作点是电池电弧延迟功能（CADF）上的一个点。使用小区的CADF上的所选择的操作点为每个小区确定f-sigma延迟值。然后可以将定时路径中的多个小区的确定的延迟值组合以预测整个定时路径的估计延迟。该方法可以扩展以处理压摆率，预测保持时间统计，修剪路径和处理收敛路径。

8. 发明申请

US20110216619A1 MEMORY POWER MANAGEMENT SYSTEMS AND METHODS 审中-公开
标题翻译：存储电源管理系统和方法
公开(公告)号：US20110216619A1
公开(公告)日：2011-09-08
申请号：US13106612
申请日：2011-05-12
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

9. 发明授权

US07793119B2 Adaptive voltage scaling with age compensation 有权
标题翻译：适应电压调整与年龄补偿
公开(公告)号：US07793119B2
公开(公告)日：2010-09-07
申请号：US11643194
申请日：2006-12-21
申请人： Gordon Gammie , Alice Wang , Hugh Thomas Mair
发明人： Gordon Gammie , Alice Wang , Hugh Thomas Mair
IPC分类号： G06F1/00 , G06F1/32 , G06F17/50
CPC分类号： G06F1/26
摘要： One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one target performance circuit comprising a first semiconductor material and being configured to determine at least one voltage potential in response to achieving a target performance based on an applied voltage. The system also comprises a controller configured to set an output of a variable power supply to the determined at least one voltage potential, and an aging controller configured to control the at least one target performance circuit to age the first semiconductor material at a rate that is at least substantially commensurate with a rate at which other circuitry in the IC ages.
摘要翻译：本发明的一个实施例包括与集成电路（IC）相关联的自适应电压缩放系统。该系统包括至少一个目标性能电路，其包括第一半导体材料并被配置为响应于基于所施加的电压实现目标性能来确定至少一个电压电位。该系统还包括控制器，该控制器被配置为将可变电源的输出设置为所确定的至少一个电压电位;以及老化控制器，其被配置为控制所述至少一个目标性能电路以使所述第一半导体材料以至少基本上与IC中的其它电路的寿命相当。

10. 发明申请

US20090039952A1 System and Method for Auto-Power Gating Synthesis for Active Leakage Reduction 有权
标题翻译：用于主动泄漏减少的自动门控合成系统和方法
公开(公告)号：US20090039952A1
公开(公告)日：2009-02-12
申请号：US11947012
申请日：2007-11-29
申请人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
发明人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
IPC分类号： G05F1/10 , G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.
摘要翻译：一种方法包括解析集成电路的设计以定义自动功率选通电源域中的单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线生成集成电路的布局。解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

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