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1. 发明授权

US08278980B1 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode 有权
公开(公告)号：US08278980B1
公开(公告)日：2012-10-02
申请号：US13484472
申请日：2012-05-31
申请人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

2. 发明授权

US07809961B2 Standby mode for power management 有权
标题翻译：待机模式进行电源管理
公开(公告)号：US07809961B2
公开(公告)日：2010-10-05
申请号：US11559388
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F1/00 , G06F3/038 , H04B7/185 , H04B1/04 , H04B1/16 , H04B7/00 , H04B1/38 , G09G3/18 , G11C5/14
CPC分类号： G06F1/3237 , G06F1/3228 , Y02D10/128 , Y02D50/20
摘要： An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes an initiator module coupled to a power and clock control module (PCCM). When the initiator module meets conditions for standby mode, the initiator module sends a standby signal to the PCCM and does not interact with other initiator, target, or interconnect modules. When the PCCM communicates a wait signal, the initiator module enters standby mode. When the initiator module detects a wakeup event, the standby signal is deactivated. In this state, the initiator module may process information but may not interact with other modules. When the PCCM deactivates the wait signal and returns power and clock signal to steady state levels, initiator module may resume normal operation.
摘要翻译：一种用于控制电子设备中的待机模式的装置和方法。在待机模式下，电源和时钟信号被减少或停止以节省电力。该装置包括耦合到电源和时钟控制模块（PCCM）的启动器模块。当启动器模块满足待机模式条件时，启动器模块向PCCM发送备用信号，不与其他启动器，目标或互连模块进行交互。当PCCM通信等待信号时，启动器模块进入待机模式。当启动器模块检测到唤醒事件时，待机信号被禁用。在这种状态下，启动器模块可以处理信息，但是可能不与其他模块进行交互。当PCCM关闭等待信号并将电源和时钟信号恢复到稳定状态时，启动器模块可以恢复正常工作。

3. 发明申请

US20080162980A1 Memory Controller Idle Mode 有权
标题翻译：内存控制器空闲模式
公开(公告)号：US20080162980A1
公开(公告)日：2008-07-03
申请号：US11948844
申请日：2007-11-30
申请人： Franck Dahan , Gilles Dubost , Sylvain Dubois
发明人： Franck Dahan , Gilles Dubost , Sylvain Dubois
IPC分类号： G06F5/06 , G06F12/00
CPC分类号： G06F13/1694 , Y02D10/14
摘要： An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).
摘要翻译：一种用于动态修改电子设备中的存储器控制器的一个或多个操作条件的装置和方法。操作条件可以包括时钟频率和功率，其可以被修改或去除。操作条件的动态修改可以用于优化诸如功率消耗之类的参数的目的。称为空闲模式的模式可以用作存储器控制器的过渡或操作模式。存储器控制器的性能可以根据其操作条件的变化而动态变化。因此，存储器控制器可以包括操作的多种模式或子模式。存储器控制器的性能可以取决于其控制的存储器的类型，例如双数据速率（DDR）动态随机存取存储器（DRAM）。

4. 发明申请

US20050041803A1 On-device random number generator 审中-公开
标题翻译：设备上随机数发生器
公开(公告)号：US20050041803A1
公开(公告)日：2005-02-24
申请号：US10643069
申请日：2003-08-18
申请人： Alain Chateau , Franck Dahan
发明人： Alain Chateau , Franck Dahan
IPC分类号： G06F7/58 , G06F21/73 , H04L9/00
CPC分类号： G06F21/73 , G06F7/58
摘要： A random key generator circuit (10) generates a random number internal to an integrated circuit and stores the random number as a “root key” in a memory (18) on the integrated circuit. The output of the Root Key memory (18) is only accessible internal to the integrated circuit. The root key can be permanently stored in a fused memory or other memory type which is protected from erasure or reprogramming once the root key is stored.
摘要翻译：随机密钥生成器电路（10）生成集成电路内部的随机数，并将随机数作为“根密钥”存储在集成电路的存储器（18）中。根密钥存储器（18）的输出只能在集成电路内部访问。根密钥可以永久存储在融合存储器或其他存储器类型中，一旦存储了根密钥，该密钥将被保护而不被擦除或重新编程。

5. 发明授权

US08207764B2 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode 有权
标题翻译：使用动态电压和频率缩放和数字锁相环高速旁路模式增强电源管理
公开(公告)号：US08207764B2
公开(公告)日：2012-06-26
申请号：US12607981
申请日：2009-10-28
申请人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
摘要翻译：一种用于时钟/电压缩放的装置包括：设备功率管理器，被布置为向接口提供可缩放的频率时钟; 由恒定的固定频率时钟和恒定电压提供的延迟锁定环路，被布置成根据过程，电压和/或温度产生唯一的代码; 以及耦合到所述延迟锁定环路的受控延迟线路元件，被布置为基于所述唯一码产生适当的延迟数据选通。一种用于数字锁相环高速旁路模式的方法包括在第一高速时钟域中提供第一数字锁相环; 在第二时钟域中提供第二数字锁相环; 使用本地同步的设备电源管理器根据预选设置来控制第一无毛刺多路复用器的输出; 以及使用所述第二数字锁相环的控制逻辑元件来控制第二无毛刺多路复用器的输出。

6. 发明授权

US08055828B2 Electronic power management system 有权
标题翻译：电子电源管理系统
公开(公告)号：US08055828B2
公开(公告)日：2011-11-08
申请号：US13028440
申请日：2011-02-16
申请人： Gregory R. Conti , Franck Dahan
发明人： Gregory R. Conti , Franck Dahan
IPC分类号： G06F13/24 , G06F1/26
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.
摘要翻译：一种电子电源管理系统，包括可在不同安全性和上下文相关模式下操作的多个处理器，并且具有相应的电源电压输入和时钟输入，所述处理器具有至少一个中断输入和至少一个等待中断输出。该系统还包括功率控制电路，其可操作以可配置地调节所述电源电压输入和时钟输入的电源电压和时钟速率。所述系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器中的至少一个可操作以响应于所述中断信号配置所述功率控制电路。

7. 发明申请

US20110145460A1 PROCESSING SYSTEM OPERABLE IN VARIOUS EXECUTION ENVIRONMENTS 有权
标题翻译：处理系统可在各种执行环境中运行
公开(公告)号：US20110145460A1
公开(公告)日：2011-06-16
申请号：US13028416
申请日：2011-02-16
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.
摘要翻译：可在各种执行环境中操作的处理系统。该系统包括具有各自的中断输入的多个处理器核，各自等待中断输出和相应的安全输出。该系统还包括耦合到至少一个处理器核心的寄存器，用于识别主动执行环境。该系统还包括全局中断处理器，其可操作以选择性地将中断路由到所述多个处理器核的一个或多个中断输入。该系统还包括具有多个中断相关输出线的转换电路，并且所述转换电路馈送至少一些所述相应的等待中断输出和相应的安全输出并由所述寄存器馈送。

8. 发明授权

US08458429B2 Memory controller idle mode 有权
标题翻译：内存控制器空闲模式
公开(公告)号：US08458429B2
公开(公告)日：2013-06-04
申请号：US11948844
申请日：2007-11-30
申请人： Franck Dahan , Gilles Dubost , Sylvain Dubois
发明人： Franck Dahan , Gilles Dubost , Sylvain Dubois
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/00 , G06F1/26 , G06F1/32 , G06F11/30 , G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： G06F13/1694 , Y02D10/14
摘要： An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).
摘要翻译：一种用于动态修改电子设备中的存储器控制器的一个或多个操作条件的装置和方法。操作条件可以包括时钟频率和功率，其可以被修改或去除。操作条件的动态修改可以用于优化诸如功率消耗之类的参数的目的。称为空闲模式的模式可以用作存储器控制器的过渡或操作模式。存储器控制器的性能可以根据其操作条件的变化而动态变化。因此，存储器控制器可以包括操作的多种模式或子模式。存储器控制器的性能可以取决于其控制的存储器的类型，例如双数据速率（DDR）动态随机存取存储器（DRAM）。

9. 发明申请

US20110095794A1 Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode 有权
标题翻译：使用动态电压和频率缩放和数字锁相环高速旁路模式增强电源管理
公开(公告)号：US20110095794A1
公开(公告)日：2011-04-28
申请号：US12607981
申请日：2009-10-28
申请人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
摘要翻译：一种用于时钟/电压缩放的装置包括：设备功率管理器，被布置为向接口提供可缩放的频率时钟; 由恒定的固定频率时钟和恒定电压提供的延迟锁定环路，被布置成根据过程，电压和/或温度产生唯一的代码; 以及耦合到所述延迟锁定环路的受控延迟线路元件，被布置为基于所述唯一码产生适当的延迟数据选通。一种用于数字锁相环高速旁路模式的方法包括在第一高速时钟域中提供第一数字锁相环; 在第二时钟域中提供第二数字锁相环; 使用本地同步的设备电源管理器根据预选设置来控制第一无毛刺多路复用器的输出; 以及使用所述第二数字锁相环的控制逻辑元件来控制第二无毛刺多路复用器的输出。

10. 发明申请

US20080307240A1 POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE 审中-公开
标题翻译：电力管理电子电路，系统及其制造方法和工艺
公开(公告)号：US20080307240A1
公开(公告)日：2008-12-11
申请号：US11760263
申请日：2007-06-08
申请人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
发明人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/06 , G06F1/08 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F21/79 , Y02D10/126 , Y02D10/128 , Y02D10/172 , Y02D50/20
摘要： An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).
摘要翻译：一种电子电路，包括功率管理电路（2610）和耦合到功率管理电路（2610）的功率管理控制电路（3570），并且可操作以在至少第一操作性能点（OPP1）和第二较高操作功率管理电路（2610）的性能点（OPP2），每个性能点包括电压和工作频率的相应对（Vn，Fn），并且功率管理控制电路（3570）还可操作以控制功率管理电路功率管理电路（2610），其中在给定操作性能点处的功率管理电路（2610）具有静态功耗（4820.1），并且动态功率开关将功率管理电路置于较低的静态功率状态 4860.1），功耗比静态功耗（4820.1）要低。

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