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1. 发明授权

US06903780B2 Method of expanding high-speed serial video data providing compatibility with a class of DVI receivers 有权
标题翻译：扩展与一类DVI接收机兼容的高速串行视频数据的方法
公开(公告)号：US06903780B2
公开(公告)日：2005-06-07
申请号：US09966167
申请日：2001-09-28
申请人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
发明人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
IPC分类号： G09G5/00 , H03M7/30 , H04L25/49 , H04N7/24 , H04N7/26 , H04N7/04
CPC分类号： G09G5/006 , H03M7/30 , H04L25/4908 , H04N7/24 , H04N19/184
摘要： A method of expanding data to a high-speed serial video link in such a way that it is invisible to existing receivers and such that auxiliary data, i.e. audio data, can be transmitted without any knowledge of the capabilities of the display to receive the auxiliary data.
摘要翻译：一种将数据扩展到高速串行视频链路的方式，使得现有接收机不可见，并且可以传输辅助数据（即，音频数据），而无需了解显示器的能力来接收辅助信号数据。

2. 发明授权

US06633243B2 Method of encoding video data for serial transmission 有权
标题翻译：编码串行传输的视频数据的方法
公开(公告)号：US06633243B2
公开(公告)日：2003-10-14
申请号：US09953803
申请日：2001-09-17
申请人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
发明人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
IPC分类号： H03M700
CPC分类号： G09G5/006 , H03M7/14 , H04L25/4908 , H04N19/184
摘要： An encoding scheme simplifies the TMDS encoding algorithm described in the DVI 1.0 specification while retaining compatibility with most existing DVI receivers. The generation of the Transition Control bit has been removed; and although the INV bit has a similar function to the DC bit in the DVI 1.0 standard, the algorithm for deriving it is very different. No attempt is made to maintain a DC balance on the cable. Instead, the INV bit is set to a ‘1’ for the purpose of removing ‘rogue’ character sequences; otherwise it is always set to a ‘0’.
摘要翻译：编码方案简化了DVI 1.0规范中描述的TMDS编码算法，同时保留了与大多数现有DVI接收器的兼容性。过渡控制位的生成已被删除; 虽然INV位具有与DVI 1.0标准中的DC位相似的功能，但是用于推导它的算法是非常不同的。不要在电缆上维持直流平衡。相反，为了消除“流氓”字符序列，将INV位设置为“1” 否则始终设置为“0”。

3. 发明授权

US10275010B2 Fast and Autonomous mechanism for CPU OC protection 有权
公开(公告)号：US10275010B2
公开(公告)日：2019-04-30
申请号：US15119731
申请日：2015-02-16
申请人： MediaTek Singapore Pte. Ltd. , Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32 , G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

4. 发明申请

US20170068296A1 Fast and Autonomous Mechanism for CPU OC Protection 审中-公开
标题翻译：快速自主的CPU OC保护机制
公开(公告)号：US20170068296A1
公开(公告)日：2017-03-09
申请号：US15119731
申请日：2015-02-16
申请人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist , MediaTek Singapore Pte. Ltd.
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
摘要翻译：提供了一种检测和防止过电流引起的系统故障的方法。 OC保护控制器根据接收到的CPU活动信息监视CPU总功耗。响应监视，如果CPU功耗超过阈值，则OC保护控制器输出频率抖动控制信号，以降低CPU时钟频率，使CPU不达到OC限制。 OC保护控制器还输出PLL频率控制信号，以减少PLL时钟频率，提高系统效率。

5. 发明授权

US07633314B2 System and method for reducing power-on-transient current magnitude 有权
标题翻译：用于降低功率瞬态电流幅度的系统和方法
公开(公告)号：US07633314B2
公开(公告)日：2009-12-15
申请号：US11563868
申请日：2006-11-28
申请人： Hugh Mair , Rolf Lagerquist
发明人： Hugh Mair , Rolf Lagerquist
IPC分类号： H03K19/096
CPC分类号： H03K17/164
摘要： System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
摘要翻译：用于降低分布式报头交换机上的上电瞬态电流幅度的系统和方法。优选实施例包括将电路耦合到电源的分布式头部开关，分配的头部开关包括线性顺序的组合开关，每个组合开关包含预充电开关和头部开关。一次通过涉及顺序打开每个预充电开关，这使得分配的标头开关处的电压电平接近最终电压电平的电压电平，而第二次通过涉及顺序地接通每个标头开关。由于分布式标题开关处的电压电平接近最终的电压电平，所以产生的瞬态电流的幅度很小。

6. 发明授权

US06570415B2 Reduced voltage swing digital differential driver 有权
公开(公告)号：US06570415B2
公开(公告)日：2003-05-27
申请号：US10158659
申请日：2002-05-30
申请人： Hao Chen , Rolf Lagerquist , Hugh Mair
发明人： Hao Chen , Rolf Lagerquist , Hugh Mair
IPC分类号： H03B100
CPC分类号： H04L25/0272 , H03K17/04106 , H03K17/04123 , H03K19/0013 , H03K2217/0036 , H04L25/028
摘要： A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.

7. 发明申请

US20070120578A1 Integrated Header Switch with Low-Leakage PMOS and High-Leakage NMOS Transistors 审中-公开
标题翻译：具有低泄漏PMOS和高泄漏NMOS晶体管的集成头开关
公开(公告)号：US20070120578A1
公开(公告)日：2007-05-31
申请号：US11564405
申请日：2006-11-29
申请人： Hugh Mair , David Scott , Rolf Lagerquist
发明人： Hugh Mair , David Scott , Rolf Lagerquist
IPC分类号： H03K19/094
CPC分类号： H03K17/6872 , H03K19/0013 , H03K19/00315 , H03K2217/0036
摘要： System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.
摘要翻译：为集成电路中的电路提供大的导通电流和小的截止电流的系统和方法。优选实施例包括用于向由PMOS晶体管和并联的NMOS晶体管制成的集成电路中的电路提供功率的开关。每个晶体管的栅极端子耦合到单独的控制信号线。 PMOS晶体管以高电压电源电平向电路提供电流，而NMOS晶体管以低电压电源电平向电路提供电流，其中可以在设计期间改变PMOS和NMOS晶体管的尺寸以满足功率需求。根据功率要求，可以使用多个PMOS和NMOS晶体管。 PMOS和NMOS晶体管的组合允许使用有限的制造工艺，其中可以限制晶体管宽度。

8. 发明申请

US20060049849A1 System and method for reducing power-on transient current magnitude 有权
公开(公告)号：US20060049849A1
公开(公告)日：2006-03-09
申请号：US10933550
申请日：2004-09-03
申请人： Hugh Mair , Rolf Lagerquist
发明人： Hugh Mair , Rolf Lagerquist
IPC分类号： H03K19/096
CPC分类号： H03K17/164
摘要： System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.

9. 发明申请

US20070103202A1 System and Method for Reducing Power-On-Transient Current Magnitude 有权
标题翻译：降低上电瞬时电流幅度的系统和方法
公开(公告)号：US20070103202A1
公开(公告)日：2007-05-10
申请号：US11563868
申请日：2006-11-28
申请人： Hugh Mair , Rolf Lagerquist
发明人： Hugh Mair , Rolf Lagerquist
IPC分类号： H03K19/096
CPC分类号： H03K17/164
摘要： System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
摘要翻译：用于降低分布式报头交换机上的上电瞬态电流幅度的系统和方法。优选实施例包括将电路耦合到电源的分布式头部开关，分配的头部开关包括线性顺序的组合开关，每个组合开关包含预充电开关和头部开关。一次通过涉及顺序打开每个预充电开关，这使得分配的标头开关处的电压电平接近最终电压电平的电压电平，而第二次通过涉及顺序地接通每个标头开关。由于分布式标题开关处的电压电平接近最终的电压电平，所以产生的瞬态电流的幅度很小。

10. 发明申请

US20060033525A1 Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors 有权
标题翻译：具有低泄漏PMOS和高泄漏NMOS晶体管的集成标头开关
公开(公告)号：US20060033525A1
公开(公告)日：2006-02-16
申请号：US10916135
申请日：2004-08-11
申请人： Hugh Mair , David Scott , Rolf Lagerquist
发明人： Hugh Mair , David Scott , Rolf Lagerquist
IPC分类号： H03K19/003
CPC分类号： H03K17/6872 , H03K19/0013 , H03K19/00315 , H03K2217/0036
摘要： System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.
摘要翻译：为集成电路中的电路提供大的导通电流和小的截止电流的系统和方法。优选实施例包括用于向由PMOS晶体管和并联的NMOS晶体管制成的集成电路中的电路提供功率的开关。每个晶体管的栅极端子耦合到单独的控制信号线。 PMOS晶体管以高电压电源电平向电路提供电流，而NMOS晶体管以低电压电源电平向电路提供电流，其中可以在设计期间改变PMOS和NMOS晶体管的尺寸以满足功率需求。根据功率要求，可以使用多个PMOS和NMOS晶体管。 PMOS和NMOS晶体管的组合允许使用有限的制造工艺，其中可以限制晶体管宽度。

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