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1. 发明授权

US08117568B2 Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design 有权
标题翻译：集成电路设计中制造效果快速仿真的装置，方法和计算机程序产品
公开(公告)号：US08117568B2
公开(公告)日：2012-02-14
申请号：US12237727
申请日：2008-09-25
申请人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
发明人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5009 , G06F2217/12 , Y02P90/265
摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
摘要翻译：方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。

2. 发明申请

US20100077372A1 Apparatus, Method and Computer Program Product for Fast Stimulation of Manufacturing Effects During Integrated Circuit Design 有权
标题翻译：集成电路设计中快速刺激制造效果的装置，方法和计算机程序产品
公开(公告)号：US20100077372A1
公开(公告)日：2010-03-25
申请号：US12237727
申请日：2008-09-25
申请人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
发明人： Hua Xiang , Laertis Economikos , Mohammed F. Fayaz , Stephen E. Greco , Patricia A. O'Neil , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/12 , Y02P90/265
摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
摘要翻译：方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。

3. 发明授权

US08143166B2 Polishing method with inert gas injection 有权
标题翻译：惰性气体注入抛光方法
公开(公告)号：US08143166B2
公开(公告)日：2012-03-27
申请号：US12046151
申请日：2008-03-11
申请人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
发明人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
IPC分类号： H01L21/461
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.
摘要翻译：在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

4. 发明申请

US20090233444A1 POLISHING METHOD WITH INERT GAS INJECTION 有权
标题翻译：具有惰性气体注入的抛光方法
公开(公告)号：US20090233444A1
公开(公告)日：2009-09-17
申请号：US12046151
申请日：2008-03-11
申请人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
发明人： Feng Zhao , Wu Ping Liu , John Sudijono , Laertis Economikos , Lawrence A. Clevenger
IPC分类号： H01L21/306 , C09K13/00
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.
摘要翻译：在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

5. 发明申请

US20080051008A1 APPARATUS AND METHOD FOR CHEMICAL MECHANICAL POLISHING WITH IMPROVED UNIFORMITY 审中-公开
标题翻译：具有改进均匀性的化学机械抛光的装置和方法
公开(公告)号：US20080051008A1
公开(公告)日：2008-02-28
申请号：US11466133
申请日：2006-08-22
申请人： Laertis Economikos , Deok-Kee Kim , Byeongju Park
发明人： Laertis Economikos , Deok-Kee Kim , Byeongju Park
IPC分类号： B24B49/00 , B24B7/30 , B24B29/00
CPC分类号： B24B37/042 , B24B1/005
摘要： A chemical mechanical polishing (CMP) apparatus includes a workpiece carrier configured for retaining a workpiece thereupon, a polishing platen configured for retaining a polishing pad thereupon, and an electromagnetic coil surrounding a periphery of the workpiece carrier. The electromagnetic coil is configured to provide a magnetic field of alternating polarity to cause the rotation of ferromagnetic slurry particles disposed on the workpiece to facilitate polishing of the workpiece.
摘要翻译：化学机械抛光（CMP）装置包括构造成用于保持其上的工件的工件载体，被配置为用于将抛光垫保持在其上的抛光台和围绕工件载体的周边的电磁线圈。电磁线圈被配置成提供具有交替极性的磁场，以引起设置在工件上的铁磁性浆料颗粒的旋转，以便于抛光工件。

6. 发明申请

US20050079709A1 PLANARIZATION SYSTEM AND METHOD USING A CARBONATE CONTAINING FLUID 失效
标题翻译：使用含有碳酸盐的流化床系统和方法
公开(公告)号：US20050079709A1
公开(公告)日：2005-04-14
申请号：US10605610
申请日：2003-10-13
申请人： Donald Delehanty , James Hannah , Daniel Heenan , Fen Jamin , Laertis Economikos
发明人： Donald Delehanty , James Hannah , Daniel Heenan , Fen Jamin , Laertis Economikos
IPC分类号： B24B7/22 , B24B37/04 , C09G1/04 , H01L21/302 , H01L21/3105 , H01L21/461
CPC分类号： C09G1/04 , B24B7/228 , H01L21/31053
摘要： Disclosed herein are a system and method of polishing a layer of a substrate. The disclosed method includes providing a polishing apparatus adapted to impart relative movement between a polishing pad and a substrate having a first layer to be polished; providing a liquid medium having a pH between 4 and 11 to an interface between the substrate and the polishing pad, the liquid medium including a pH controlling substance including at least one of an acid and a base, a carbonate and a stabilizer additive comprising at least one selected from the group consisting of amino acids and polyacrylic acid; and moving at least one of the substrate and the polishing pad relative to the other to polish the layer of the substrate.
摘要翻译：本文公开了一种抛光衬底层的系统和方法。所公开的方法包括提供适于在抛光垫和具有要抛光的第一层的基底之间施加相对运动的抛光装置; 提供pH在4和11之间的液体介质到基底和抛光垫之间的界面，液体介质包括pH控制物质，其包括酸和碱中的至少一种，碳酸盐和稳定剂添加剂，至少包括一个选自氨基酸和聚丙烯酸; 并且相对于另一个移动衬底和抛光垫中的至少一个以抛光衬底的层。

7. 发明授权

US06794242B1 Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts 有权
标题翻译：用于DRAM阵列和栅极互连的改进的顶部氧化物层，同时提供自对准栅极触点的可扩展工艺
公开(公告)号：US06794242B1
公开(公告)日：2004-09-21
申请号：US09675435
申请日：2000-09-29
申请人： Thomas W. Dyer , Andreas Knorr , Laertis Economikos , Scott Halle , Rajeev Malik , Norbert Arnod
发明人： Thomas W. Dyer , Andreas Knorr , Laertis Economikos , Scott Halle , Rajeev Malik , Norbert Arnod
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10891
摘要： A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.
摘要翻译：如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。顶部氧化物通过首先形成垂直装置而形成，其中衬垫氮化物保持就位。一旦器件已经形成并且栅极多晶硅已经被平坦化到衬底氮化物的表面之下，衬垫氮化物被剥离掉，留下栅极多晶硅插塞的顶部延伸到活性硅表面之上。这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。沉积的顶部氧化物填充多晶硅插塞之间和之上的区域。顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

8. 发明授权

US06656817B2 Method of filling isolation trenches in a substrate 失效
标题翻译：在衬底中填充隔离沟槽的方法
公开(公告)号：US06656817B2
公开(公告)日：2003-12-02
申请号：US10136097
申请日：2002-04-30
申请人： Ramachandra Divakaruni , Laertis Economikos , Byeong Y. Kim
发明人： Ramachandra Divakaruni , Laertis Economikos , Byeong Y. Kim
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/763
摘要： Disclosed herein is a method of filling isolation trenches in a substrate. The method includes anisotropically etching trenches in a surface of a substrate and partially filling the trenches with a deposited oxide. As a consequence of the deposition, the oxide accumulates in mounds on the surface between trenches. The trenches are then filled with a supporting material of a highly flowable material such as anti-reflective coating (ARC), low-K dielectric, or a spin-on-polymer, or alternatively, a supporting material of polysilicon. A flattening process is then applied to lower the mound topography. The supporting material is then removed and the filling of the trenches with oxide is then continued. When polysilicon is used as the supporting material, the mounds are removed by wet etching prior to removing the polysilicon.
摘要翻译：本文公开了一种在衬底中填充隔离沟槽的方法。该方法包括在衬底的表面中各向异性蚀刻沟槽，并用沉积的氧化物部分地填充沟槽。作为沉积的结果，氧化物堆积在沟槽之间的表面上的土堆中。然后用诸如抗反射涂层（ARC），低K电介质或旋涂聚合物的高度可流动的材料的支撑材料或者多晶硅的支撑材料填充沟槽。然后应用扁平化过程以降低墩形地形。然后移除支撑材料，然后继续用氧化物填充沟槽。当使用多晶硅作为支撑材料时，在去除多晶硅之前通过湿法蚀刻去除土堆。

9. 发明授权

US06596580B2 Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure 有权
标题翻译： DRAM和FRAM中高k堆叠电容器的凹陷Pt结构，以及形成此结构的方法
公开(公告)号：US06596580B2
公开(公告)日：2003-07-22
申请号：US09982574
申请日：2001-10-18
申请人： Jingyu Lian , Greg Costrini , Laertis Economikos , Michael Wise
发明人： Jingyu Lian , Greg Costrini , Laertis Economikos , Michael Wise
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L27/10855
摘要： The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.
摘要翻译：将底层电极和阻挡层之间的界面暴露于高温氧气环境下，通过原位沉积有阻挡层的Pt进行避免。

10. 发明授权

US06403412B1 Method for in-situ formation of bottle shaped trench by gas phase etching 失效
标题翻译：通过气相蚀刻原位形成瓶形沟槽的方法
公开(公告)号：US06403412B1
公开(公告)日：2002-06-11
申请号：US09304291
申请日：1999-05-03
申请人： Laertis Economikos , Byeongju Park
发明人： Laertis Economikos , Byeongju Park
IPC分类号： H01L218234
CPC分类号： H01L27/1087 , H01L21/3065 , H01L21/76232
摘要： A method fabricates a bottle shaped trench by providing a substrate with a substantially vertical trench therein and a collar about an upper interior portion of the trench and isotropically HCl etching a lower interior portion of the trench under the collar for expansion thereof, wherein the expanded lower interior portion has a wider cross section than that of the upper interior portion of the trench. Further, the method performs potential in-situ process integration with a gas phase doping in the same tool as the one that performed the gas phase etching process.
摘要翻译：一种方法是通过在其中提供基本上垂直的沟槽的衬底和围绕沟槽的上部内部的套环来制造瓶形沟槽，并且各向同性地在衬套下蚀刻沟槽的下部内部以使其膨胀，其中扩大的下部内部部分具有比沟槽的上部内部部分更宽的横截面。此外，该方法在与执行气相蚀刻工艺的工具相同的工具中进行与气相掺杂的潜在的原位工艺集成。

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