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1. 发明授权

US06847098B1 Non-floating body device with enhanced performance 有权
标题翻译：非浮体装置具有增强的性能
公开(公告)号：US06847098B1
公开(公告)日：2005-01-25
申请号：US10641575
申请日：2003-08-14
申请人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10 , H01L23/58 , H01L24/06
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer. Subsequent silicon oxide deposition and planarization procedures results in a first portion of the strained silicon layer overlying the silicon alloy layer while a second portion overlays a buried oxide region. A semiconductor device is then formed in the strained silicon layer, with specific elements of the semiconductor device located on a buried oxide region.
摘要翻译：已经开发了在半导体衬底中形成掩埋氧化硅区域的方法，其中形成在应变硅形状的部分下方的掩埋氧化硅区域的部分以及应变硅形状用于容纳半导体器件的方法。本发明的第一实施例的特征在于通过热氧化工艺在硅合金层中形成的掩埋氧化物区域。在热氧化过程中保护的应变硅层的第一部分覆盖硅合金层，而应变硅层的第二部分覆盖掩埋氧化物区域。本发明的第二实施例的特征在于用于在硅合金层中形成各向同性开口的各向同性干法蚀刻程序，其中开口横向延伸在应变硅层的一部分下方。随后的氧化硅沉积和平坦化过程导致覆盖硅合金层的应变硅层的第一部分，而第二部分覆盖掩埋氧化物区域。然后在应变硅层中形成半导体器件，其中半导体器件的特定元件位于掩埋氧化物区域上。

2. 发明申请

US20050156156A1 Method of fabricating a non-floating body device with enhanced performance 有权
标题翻译：制造具有增强性能的非浮体装置的方法
公开(公告)号：US20050156156A1
公开(公告)日：2005-07-21
申请号：US11032403
申请日：2005-01-10
申请人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.
摘要翻译：提供了一种半导体晶体管器件，其包括具有至少两个区域的衬底，延伸到衬底的第一表面的半导体区域和延伸到衬底的第二表面的绝缘区域。半导体晶体管器件还包括覆盖在衬底的两个表面上的图案化半导体结构。图案化的半导体结构包括覆盖在衬底的第二表面上的源极或漏极区域。半导体晶体管器件还包括覆盖图案化半导体结构的图案化栅极结构。

3. 发明授权

US06627515B1 Method of fabricating a non-floating body device with enhanced performance 有权
标题翻译：制造具有增强性能的非浮体装置的方法
公开(公告)号：US06627515B1
公开(公告)日：2003-09-30
申请号：US10318471
申请日：2002-12-13
申请人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L2176
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer. Subsequent silicon oxide deposition and planarization procedures results in a first portion of the strained silicon layer overlying the silicon alloy layer while a second portion overlays a buried oxide region. A semiconductor device is then formed in the strained silicon layer, with specific elements of the semiconductor device located on a buried oxide region.
摘要翻译：已经开发了在半导体衬底中形成掩埋氧化硅区域的方法，其中形成在应变硅形状的部分下方的掩埋氧化硅区域的部分以及应变硅形状用于容纳半导体器件的方法。本发明的第一实施例的特征在于通过热氧化工艺在硅合金层中形成的掩埋氧化物区域。在热氧化过程中保护的应变硅层的第一部分覆盖硅合金层，而应变硅层的第二部分覆盖掩埋氧化物区域。本发明的第二实施例的特征在于用于在硅合金层中形成各向同性开口的各向同性干法蚀刻程序，其中开口横向延伸在应变硅层的一部分下方。随后的氧化硅沉积和平坦化过程导致覆盖硅合金层的应变硅层的第一部分，而第二部分覆盖掩埋氧化物区域。然后在应变硅层中形成半导体器件，其中半导体器件的特定元件位于掩埋氧化物区域上。

4. 发明申请

US20090155965A1 METHOD OF FABRICATING A NON-FLOATING BODY DEVICE WITH ENHANCED PERFORMANCE 有权
标题翻译：制造具有增强性能的非浮动体装置的方法
公开(公告)号：US20090155965A1
公开(公告)日：2009-06-18
申请号：US12391307
申请日：2009-02-24
申请人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L21/336 , H01L21/762 , H01L21/76
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxide region.
摘要翻译：提供了一种方法，其包括在半导体衬底上形成第一半导体层，在第一半导体层上生长第二半导体层，在第一半导体层上形成复合形状，每个复合形状包括上覆氧化物形状和基底第二半导体形状，第一半导体层的部分暴露在复合形状之间，在复合形状的侧面上形成间隔物，在第一半导体层的暴露的顶部形成掩埋的氧化硅区域，并且在第一半导体层的部分位置潜在的第二半导体形状，选择性地去除导致第二半导体形状的耐氧化形状和间隔物，以及形成第二半导体形状的半导体器件，其中半导体器件的第一部分覆盖第一半导体层，并且其中第二部分半导体器件叠加 y是一个埋置的氧化硅区域。

5. 发明授权

US07625806B2 Method of fabricating a non-floating body device with enhanced performance 有权
标题翻译：制造具有增强性能的非浮体装置的方法
公开(公告)号：US07625806B2
公开(公告)日：2009-12-01
申请号：US12391307
申请日：2009-02-24
申请人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxide region.
摘要翻译：提供了一种方法，其包括在半导体衬底上形成第一半导体层，在第一半导体层上生长第二半导体层，在第一半导体层上形成复合形状，每个复合形状包括上覆氧化物形状和基底第二半导体形状，第一半导体层的部分暴露在复合形状之间，在复合形状的侧面上形成间隔物，在第一半导体层的暴露的顶部形成掩埋的氧化硅区域，并且在第一半导体层的部分位置潜在的第二半导体形状，选择性地去除导致第二半导体形状的耐氧化形状和间隔物，以及形成第二半导体形状的半导体器件，其中半导体器件的第一部分覆盖第一半导体层，并且其中第二部分半导体器件叠加 y是一个埋置的氧化硅区域。

6. 发明授权

US07514730B2 Method of fabricating a non-floating body device with enhanced performance 有权
标题翻译：制造具有增强性能的非浮体装置的方法
公开(公告)号：US07514730B2
公开(公告)日：2009-04-07
申请号：US11032403
申请日：2005-01-10
申请人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.
摘要翻译：提供了一种半导体晶体管器件，其包括具有至少两个区域的衬底，延伸到衬底的第一表面的半导体区域和延伸到衬底的第二表面的绝缘区域。半导体晶体管器件还包括覆盖在衬底的两个表面上的图案化半导体结构。图案化的半导体结构包括覆盖在衬底的第二表面上的源极或漏极区域。半导体晶体管器件还包括覆盖图案化半导体结构的图案化栅极结构。

7. 发明授权

US06958291B2 Interconnect with composite barrier layers and method for fabricating the same 有权
标题翻译：与复合阻挡层互连及其制造方法
公开(公告)号：US06958291B2
公开(公告)日：2005-10-25
申请号：US10654757
申请日：2003-09-04
申请人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
发明人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76846
摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.
摘要翻译：复合ALD形成的扩散阻挡层。在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

8. 发明申请

US20050077627A1 Copper wiring with high temperature superconductor (HTS) layer 有权
标题翻译：铜线与高温超导体（HTS）层
公开(公告)号：US20050077627A1
公开(公告)日：2005-04-14
申请号：US10684224
申请日：2003-10-10
申请人： Chen-Hua Yu , Horng-Huei Tseng , Chenming Hu , Chao-Hsiung Wang
发明人： Chen-Hua Yu , Horng-Huei Tseng , Chenming Hu , Chao-Hsiung Wang
IPC分类号： H01L21/768 , H01L23/532 , H01L21/4763 , H01L23/48
CPC分类号： H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.
摘要翻译：使用HTS（高温超导体）层与介电材料和铜（或其它金属）导电布线之间的典型扩散层组合形成半导体器件的半导体器件和方法。 HTS层包括由氧化钡钡和稀土元素构成的超导体材料。稀土元素钇特别适合。对于具有其它半导体电路或布线之上的元件的半导体器件，在沉积覆盖层的电介质之前，在布线上沉积HTS材料的覆盖层。

9. 发明授权

US07652378B2 Aluminum-based interconnection in bond pad layer 有权
标题翻译：接合垫层中的铝基互连
公开(公告)号：US07652378B2
公开(公告)日：2010-01-26
申请号：US11582129
申请日：2006-10-17
申请人： Horng-Huei Tseng , Chenming Hu
发明人： Horng-Huei Tseng , Chenming Hu
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L23/53223 , H01L24/02 , H01L2224/04073 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： A semiconductor metal structure with an efficient usage of the chip area is provided. The structure includes a substrate, a copper-based interconnection structure over the substrate, the copper-based interconnection structure comprising a plurality of metallization layers connected by vias and in first dielectric layers, at least one aluminum-based layer over and connected to the copper-based interconnection structure, wherein a top layer of the at least one aluminum-based layer comprises a bond pad and an interconnect line connecting to two underlying vias, vias/contacts connecting a top layer of the copper-based interconnection structure and a bottom layer of the at least one aluminum-based layer, wherein the vias/contacts are in a second dielectric layer, and a third dielectric layer overlying the at least one aluminum-based layer, wherein the bond pad is exposed through an opening in the third dielectric layer.
摘要翻译：提供了一种有效利用芯片面积的半导体金属结构。该结构包括衬底，在衬底上的铜基互连结构，铜基互连结构包括通过通孔连接的多个金属化层和在第一介电层中的至少一个铝基层，并连接到铜的所述互连结构，其中所述至少一个铝基层的顶层包括接合焊盘和连接到两个底部通孔的互连线，连接铜基互连结构的顶层的通孔/触点和底层的至少一个铝基层，其中所述通孔/触点位于第二电介质层中，以及覆盖所述至少一个铝基层的第三电介质层，其中所述接合焊盘通过所述第三电介质中的开口暴露层。

10. 发明申请

US20060234438A1 Self-aligned contact for silicon-on-insulator devices 审中-公开
标题翻译：绝缘体上硅器件的自对准接触
公开(公告)号：US20060234438A1
公开(公告)日：2006-10-19
申请号：US11454600
申请日：2006-06-16
申请人： Fu-Liang Yang , Yee-Chia Yeo , Horng-Huei Tseng , Chenming Hu
发明人： Fu-Liang Yang , Yee-Chia Yeo , Horng-Huei Tseng , Chenming Hu
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L2029/7858 , H01L2924/3011
摘要： A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.
摘要翻译：一种用于形成与超薄体晶体管的自对准接触的方法，其首先提供具有由栅极叠层操作的源极和漏极区域的超薄体晶体管; 在栅极堆叠上形成接触间隔物; 形成覆盖晶体管的钝化层; 在所述钝化层中形成暴露所述接触间隔物和所述源极/漏极区域的接触孔; 用导电材料填充接触孔; 并建立与源极/漏极区域的电连通。

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