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1. 发明申请

US20060234438A1 Self-aligned contact for silicon-on-insulator devices 审中-公开
标题翻译：绝缘体上硅器件的自对准接触
公开(公告)号：US20060234438A1
公开(公告)日：2006-10-19
申请号：US11454600
申请日：2006-06-16
申请人： Fu-Liang Yang , Yee-Chia Yeo , Horng-Huei Tseng , Chenming Hu
发明人： Fu-Liang Yang , Yee-Chia Yeo , Horng-Huei Tseng , Chenming Hu
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L2029/7858 , H01L2924/3011
摘要： A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.
摘要翻译：一种用于形成与超薄体晶体管的自对准接触的方法，其首先提供具有由栅极叠层操作的源极和漏极区域的超薄体晶体管; 在栅极堆叠上形成接触间隔物; 形成覆盖晶体管的钝化层; 在所述钝化层中形成暴露所述接触间隔物和所述源极/漏极区域的接触孔; 用导电材料填充接触孔; 并建立与源极/漏极区域的电连通。

2. 发明授权

US07173305B2 Self-aligned contact for silicon-on-insulator devices 有权
标题翻译：绝缘体上硅器件的自对准接触
公开(公告)号：US07173305B2
公开(公告)日：2007-02-06
申请号：US10409810
申请日：2003-04-08
申请人： Fu-Liang Yang , Yee-Chia Yeo , Horng-Huei Tseng , Chenming Hu
发明人： Fu-Liang Yang , Yee-Chia Yeo , Horng-Huei Tseng , Chenming Hu
IPC分类号： H01L21/336 , H01L29/772
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L2029/7858 , H01L2924/3011
摘要： A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.
摘要翻译：一种用于形成与超薄体晶体管的自对准接触的方法，其首先提供具有由栅极叠层操作的源极和漏极区域的超薄体晶体管; 在栅极堆叠上形成接触间隔物; 形成覆盖晶体管的钝化层; 在所述钝化层中形成暴露所述接触间隔物和所述源极/漏极区域的接触孔; 用导电材料填充接触孔; 并建立与源极/漏极区域的电连通。

3. 发明授权

US08790970B2 Doping of semiconductor fin devices 有权
标题翻译：掺杂半导体鳍片器件
公开(公告)号：US08790970B2
公开(公告)日：2014-07-29
申请号：US11446697
申请日：2006-06-05
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

4. 发明授权

US07357838B2 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US07357838B2
公开(公告)日：2008-04-15
申请号：US11074738
申请日：2005-03-08
申请人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B23/00
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided.
摘要翻译：提供了在松弛的低缺陷密度半导体合金层（例如SiGe）上形成应变硅层的方法。

5. 发明授权

US07319258B2 Semiconductor-on-insulator chip with<100>-oriented transistors 有权
标题翻译：具有<100>取向晶体管的绝缘体上半导体芯片
公开(公告)号：US07319258B2
公开(公告)日：2008-01-15
申请号：US10901763
申请日：2004-07-28
申请人： Fu-Liang Yang , Yee-Chia Yeo , Hung-Wei Chen , Tim Tsao , Chenming Hu
发明人： Fu-Liang Yang , Yee-Chia Yeo , Hung-Wei Chen , Tim Tsao , Chenming Hu
IPC分类号： H01L21/01 , H01L21/12
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/7843 , H01L29/78654
摘要： A semiconductor-on-insulator device includes a silicon active layer with a crystal direction placed over an insulator layer. The insulator layer is placed onto a substrate with a crystal direction. Transistors oriented on a direction are formed on the silicon active layer.
摘要翻译：绝缘体上半导体器件包括布置在绝缘体层上的具有<100>晶体方向的硅有源层。将绝缘体层放置在具有<110>晶体方向的衬底上。在硅有源层上形成沿<100>方向取向的晶体管。

6. 发明申请

US20070111454A1 Gate electrode for a semiconductor fin device 有权
标题翻译：用于半导体鳍片器件的栅电极
公开(公告)号：US20070111454A1
公开(公告)日：2007-05-17
申请号：US11649453
申请日：2007-01-03
申请人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.
摘要翻译：用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。栅电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以引入和掺杂杂质的激活。在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

7. 发明授权

US07214991B2 CMOS inverters configured using multiple-gate transistors 有权
标题翻译：使用多栅极晶体管配置的CMOS反相器
公开(公告)号：US07214991B2
公开(公告)日：2007-05-08
申请号：US10313887
申请日：2002-12-06
申请人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/76
CPC分类号： H01L27/1211 , H01L21/823828 , H01L21/845 , H01L27/092 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： An inverter that includes a first multiple-gate transistor including a source connected to a power supply, a drain connected to an output terminal, and a gate electrode; a second multiple-gate transistor including a source connected to a ground, a drain connected to the output terminal, and a gate electrode; and an input terminal connected to the gate electrodes of the first and second multiple-gate transistors. Each of the first and second multiple-gate transistors may further include a semiconductor fin formed vertically on an insulating layer on top of a substrate, a gate dielectric layer overlying the semiconductor fin, and a gate electrode wrapping around the semiconductor fin separating the source and drain regions.
摘要翻译：一种逆变器，包括：第一多栅极晶体管，其包括连接到电源的源极，连接到输出端子的漏极和栅极电极; 第二多栅极晶体管，其包括连接到地的源极，连接到输出端子的漏极和栅极电极; 以及连接到第一和第二多栅极晶体管的栅电极的输入端子。第一和第二多栅极晶体管中的每一个还可以包括在衬底顶部的绝缘层上垂直形成的半导体鳍片，覆盖在半导体鳍片上的栅极电介质层，以及围绕分离源极的半导体鳍状物包围的栅电极，以及漏区。

8. 发明申请

US20060220133A1 Doping of semiconductor fin devices 有权
公开(公告)号：US20060220133A1
公开(公告)日：2006-10-05
申请号：US11446890
申请日：2006-06-05
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

9. 发明申请

US20060170053A1 Accumulation mode multiple gate transistor 审中-公开
标题翻译：累积模式多栅晶体管
公开(公告)号：US20060170053A1
公开(公告)日：2006-08-03
申请号：US10434618
申请日：2003-05-09
申请人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/78618 , H01L2029/7857
摘要： A transistor (1) having, a fin (2) and a gate electrode (3) extending on more than one side of the fin (2) to comprise more than one gate (9) of the transistor (1), and a dopant in each of a source (6), drain (7) and a channel region (8), comprising a single dopant type.
摘要翻译：一种晶体管（1），具有在鳍片（2）的多于一侧上延伸以包括晶体管（1）的多于一个栅极（9）的翅片（2）和栅电极（3），以及掺杂剂在源（6），漏极（7）和沟道区（8）的每一个中，包括单一掺杂剂类型。

10. 发明授权

US06867433B2 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
标题翻译：包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片
公开(公告)号：US06867433B2
公开(公告)日：2005-03-15
申请号：US10426566
申请日：2003-04-30
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
摘要翻译：根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

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