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1. 发明授权

US06413866B1 Method of forming a solute-enriched layer in a substrate surface and article formed thereby 有权
标题翻译：在基材表面形成富含溶质层的方法和由此形成的制品
公开(公告)号：US06413866B1
公开(公告)日：2002-07-02
申请号：US09525367
申请日：2000-03-15
申请人： Horatio S. Wildman , Lawrence A. Clevenger , Chenting Lin , Kenneth P. Rodbell , Stefan Weber , Roy C. Iggulden , Maria Ronay , Florian Schnabel
发明人： Horatio S. Wildman , Lawrence A. Clevenger , Chenting Lin , Kenneth P. Rodbell , Stefan Weber , Roy C. Iggulden , Maria Ronay , Florian Schnabel
IPC分类号： H01L2144
CPC分类号： H01L21/7685 , H01L21/321 , H01L21/76867 , H01L21/76888 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate. For microcircuit applications, the method can be used to enrich the surface of an aluminum line with elemental copper to improve the electromigration resistance of the line.
摘要翻译：一种使用最初溶解在基片材料中的溶质材料来富集基片的表面的方法，以使溶质材料在基片表面上均匀分散。该方法通常需要使用比溶质材料对选择的反应剂更具反应性的溶剂材料。使基板的表面与反应剂反应，以优先在基材的表面形成溶剂材料的反应化合物。当化合物层发展时，溶质材料从化合物层中分离或扩散到下面的衬底中，使得最接近化合物层的衬底的区域变得富集溶质材料。然后除去化合物层的至少一部分而不去除底物的下面的富集区域。对于微电路应用，该方法可用于通过元素铜来丰富铝线的表面，以提高线路的电迁移能力。

2. 发明授权

US5972787A CMP process using indicator areas to determine endpoint 有权
标题翻译： CMP过程使用指示器区域来确定端点
公开(公告)号：US5972787A
公开(公告)日：1999-10-26
申请号：US135866
申请日：1998-08-18
申请人： Karl E. Boggs , Chenting Lin , Joachim F. Nuetzel , Robert Ploessl , Maria Ronay , Florian Schnabel , Jeremy K. Stephens
发明人： Karl E. Boggs , Chenting Lin , Joachim F. Nuetzel , Robert Ploessl , Maria Ronay , Florian Schnabel , Jeremy K. Stephens
IPC分类号： H01L21/304 , B24B37/013 , B24B49/12 , H01L21/306 , H01L21/3105 , H01L21/66 , H01L23/544 , H01L21/4763 , H01L21/302 , H01L21/31
CPC分类号： B24B49/12 , B24B37/013 , H01L21/31053 , H01L22/20 , H01L22/34 , H01L2924/0002
摘要： The method of polishing metal layers on wafers comprises the steps of: providing indicator areas on said wafer, said indicator areas having combinations of line widths and pattern factors violating existing ground rules of metal lines thereby said indicator areas being dished out during said polishing using a chemical-mechanical polisher to polish the metal layers to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas, and adjusting the operation of the chemical-mechanical polisher in response to the inspection of the indicator areas. The indicator areas may include macroblocks comprised of a multitude of individual blocks. The wafer may be inspected by optically identifying the polishing state of to blocks in the macroblock. Additionally, the process may be automated for mass production. A feedback loop to the polisher can be formed where data from optical inspection of macroblocks on a polished wafer can be immediately fed back to the polisher in order to adjust process parameters.
摘要翻译：在晶片上抛光金属层的方法包括以下步骤：在所述晶片上提供指示器区域，所述指示器区域具有违反金属线的现有基准规则的线宽度和图案因素的组合，从而在所述抛光期间抛光所述指示器区域，化学机械抛光机抛光金属层以从中去除材料，检查晶片上的指示器区域以确定从所述区域移除的材料的量，以及响应于指示器区域的检查来调整化学机械抛光机的操作。指示器区域可以包括由多个单独块组成的宏块。可以通过光学地识别宏块中的块的抛光状态来检查晶片。此外，该方法可以自动化用于批量生产。可以形成到抛光机的反馈回路，其中来自抛光晶片上的宏块的光学检查的数据可以被立即反馈到抛光机，以便调整工艺参数。

3. 发明授权

US06339007B1 Capacitor stack structure and method of fabricating description 失效
标题翻译：电容器堆叠结构及其制造方法
公开(公告)号：US06339007B1
公开(公告)日：2002-01-15
申请号：US09562556
申请日：2000-05-02
申请人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
发明人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
IPC分类号： H01L2120
CPC分类号： H01L28/75 , H01L28/55 , H01L28/60
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.
摘要翻译：一种电容器结构，其包括顶部铂电极和在电极的侧壁上具有绝缘体的底部电极，并且其中底部电极从沉积相对于绝缘体在其侧壁上凹进的第一电极部分并且沉积第二绝缘体提供部分。

4. 发明授权

US06281114B1 Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication 失效
标题翻译：半导体晶圆制造后金属化学机械抛光后的平面化
公开(公告)号：US06281114B1
公开(公告)日：2001-08-28
申请号：US09498873
申请日：2000-02-07
申请人： Chenting Lin , Larry Clevenger , Ranier Florian Schnabel
发明人： Chenting Lin , Larry Clevenger , Ranier Florian Schnabel
IPC分类号： H01L21302
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/3212 , H01L21/7684 , Y02P80/30
摘要： A process is provided for planarization of an insulation layer, e.g., of silicon dioxide, on a semiconductor wafer, e.g., of silicon, and having a surface with a downwardly stepped chemically mechanically polished arrangement of metal lines in the insulation layer between intervening insulation portions. A first pattern portion of metal lines is separated by intervening insulation portions and defines a first pattern factor having a first value, and an adjacent second pattern portion of metal lines is separated by intervening insulation portions and defines a second pattern factor having a second value different from the first value. The second pattern portion is at a step depth relative to the insulation layer surface different from that of the first pattern portion relative to such layer surface. The process involves chemically mechanically polishing the insulation layer surface and first and second pattern portions to reduce the step depths of the pattern portions relative to the insulation layer surface and to each other, for planarizing the insulation layer surface and pattern portions relative to each other. The process further involves providing a further insulation layer on the planarized insulation layer, and a further arrangement of metal lines in the further insulation layer, and chemically mechanically polishing the further arrangement of metal lines.
摘要翻译：提供了一种用于在例如硅的半导体晶片上平坦化绝缘层（例如二氧化硅）的工艺，并且具有在隔离层之间的绝缘层中具有向下阶梯化学机械抛光布置的金属线的表面。金属线的第一图案部分被中间绝缘部分隔开，并且限定具有第一值的第一图案因子，并且金属线的相邻第二图案部分被中间绝缘部分隔开，并且限定具有第二值不同的第二图案因子从第一个值。第二图案部分相对于与第一图案部分相对于该层表面不同的绝缘层表面处于阶梯深度。该方法涉及对绝缘层表面和第一和第二图案部分进行化学机械抛光以减小图案部分相对于绝缘层表面和彼此的阶梯深度，以使绝缘层表面和图案部分相对于彼此平坦化。该方法还包括在平坦化的绝缘层上提供另外的绝缘层，以及在另一绝缘层中进一步布置金属线，以及化学机械抛光金属线的另外布置。

5. 发明申请

US20050023590A1 Multi-layer electrode and method of forming the same 有权
标题翻译：多层电极及其形成方法
公开(公告)号：US20050023590A1
公开(公告)日：2005-02-03
申请号：US10929157
申请日：2004-08-30
申请人： Jingyu Lian , Chenting Lin , Nicolas Nagel , Michael Wise
发明人： Jingyu Lian , Chenting Lin , Nicolas Nagel , Michael Wise
IPC分类号： H01L21/02 , H01L23/48 , H01L29/76
CPC分类号： H01L28/75 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , Y10S257/906 , Y10S257/908
摘要： A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.
摘要翻译：一种多层电极（246）及其制造方法，其中通过第一导电衬垫（240）和第二导电衬套（242）将导电区域（244）与阻挡层（222）分离。第一导电层（240）包括Pt，并且第二导电衬垫（242）包括导电氧化物的薄层。多层电极（246）防止氧扩散通过顶部导电区域（244）并且减少电极图案化期间的材料变化。

6. 发明授权

US06222220B1 Extended trench for preventing interaction between components of stacked capacitors 有权
标题翻译：扩展沟槽，用于防止堆叠电容器组件之间的相互作用
公开(公告)号：US06222220B1
公开(公告)日：2001-04-24
申请号：US09209198
申请日：1998-12-10
申请人： Chenting Lin , Andreas Knorr
发明人： Chenting Lin , Andreas Knorr
IPC分类号： H01L31119
CPC分类号： H01L27/10852
摘要： A stacked capacitor, in accordance with the present invention includes a conductive plug disposed within a trench for connecting to an access device. A barrier is formed on the plug and is disposed within the trench. A dielectric layer is formed over the trench, the dielectric layer forming a hole therethrough exposing at least a portion of the barrier. A first electrode is formed within the hole and extends from the hole. A capacitor dielectric layer is formed on the first electrode and separating the first electrode from a second electrode, and the dielectric layer and the first electrode substantially prevent chemical interactions between materials of the barrier and materials of the capacitor dielectric layer and an oxidizing environment used to form the capacitor dielectric layer. A method of fabrication is also included.
摘要翻译：根据本发明的层叠电容器包括设置在沟槽内用于连接到接入装置的导电插头。在插头上形成屏障并设置在沟槽内。在沟槽上形成电介质层，电介质层形成穿过其的至少一部分屏障的孔。第一电极形成在孔内并从孔延伸。电容器电介质层形成在第一电极上，并且将第一电极与第二电极分开，并且电介质层和第一电极基本上防止了阻挡材料和电容器介电层的材料之间的化学相互作用以及用于形成电容器介电层。还包括制造方法。

7. 发明申请

US20080108203A1 Multi-Layer Electrode and Method of Forming the Same 审中-公开
标题翻译：多层电极及其形成方法
公开(公告)号：US20080108203A1
公开(公告)日：2008-05-08
申请号：US11972147
申请日：2008-01-10
申请人： Jingyu Lian , Chenting Lin , Nicolas Nagel , Micheal Wise
发明人： Jingyu Lian , Chenting Lin , Nicolas Nagel , Micheal Wise
IPC分类号： H01L21/20 , H01L21/44
CPC分类号： H01L28/75 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , Y10S257/906 , Y10S257/908
摘要： An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.
摘要翻译：互连包括形成在电介质层中的开口。导电屏障沉积在开口中，在其上沉积第一导电层。导电氧化物沉积在第一导电层之上，并且由与第一导电层相同的材料形成的第二导电层沉积在导电衬垫上。

8. 发明授权

US06794705B2 Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials 失效
标题翻译：用于DRAM的多层Pt电极和具有高K电介质材料的FRAM
公开(公告)号：US06794705B2
公开(公告)日：2004-09-21
申请号：US09751551
申请日：2000-12-28
申请人： Jingyu Lian , Chenting Lin , Nicolas Nagel , Michael Wise
发明人： Jingyu Lian , Chenting Lin , Nicolas Nagel , Michael Wise
IPC分类号： H01L27108
CPC分类号： H01L28/75 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , Y10S257/906 , Y10S257/908
摘要： A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.
摘要翻译：一种多层电极（246）及其制造方法，其中通过第一导电衬垫（240）和第二导电衬套（242）将导电区域（244）与阻挡层（222）分离。第一导电层（240）包括Pt，并且第二导电衬垫（242）包括导电氧化物的薄层。多层电极（246）防止氧扩散通过顶部导电区域（244）并且减少电极图案化期间的材料变化。

9. 发明授权

US06685796B1 CMP uniformity 有权
标题翻译： CMP均匀性
公开(公告)号：US06685796B1
公开(公告)日：2004-02-03
申请号：US09639986
申请日：2000-08-16
申请人： Chenting Lin , Robert van den Berg , Sumit Pandey
发明人： Chenting Lin , Robert van den Berg , Sumit Pandey
IPC分类号： H01L21306
CPC分类号： B24B37/04 , B24B57/02
摘要： Improved CMP uniformity is achieved by providing improved control of the slurry distribution. Improved slurry distribution is achieved by, for example, the use of a slurry dispenser that dispenses slurry from a plurality of dispensing points. Providing a squeeze bar between the slurry dispenser and wafer to redistribute the slurry also improves the slurry distribution.
摘要翻译：通过提供浆料分布的改进控制来实现改进的CMP均匀性。通过例如使用从多个分配点分配浆料的浆料分配器来实现改进的浆料分布。在浆料分配器和晶片之间提供挤压棒以重新分配浆料也改善了浆料分布。

10. 发明授权

US06432725B1 Methods for crystallizing metallic oxide dielectric films at low temperature 有权
标题翻译：在低温下结晶金属氧化物介质膜的方法
公开(公告)号：US06432725B1
公开(公告)日：2002-08-13
申请号：US09966496
申请日：2001-09-28
申请人： Jingyu Lian , Kwong Hon Wong , Katherine Saenger , Chenting Lin
发明人： Jingyu Lian , Kwong Hon Wong , Katherine Saenger , Chenting Lin
IPC分类号： H01L2100
CPC分类号： H01L28/56 , C23C16/409 , C23C16/56 , H01L21/02197 , H01L21/0234 , H01L21/02356 , H01L21/31691
摘要： A method for forming a crystalline dielectric layer deposits an amorphous metallic oxide dielectric layer on a surface. The amorphous metallic oxide dielectric layer is treated with a plasma at a temperature of less than or equal to 400 degrees Celsius to form a crystalline layer.
摘要翻译：用于形成结晶介电层的方法在表面上沉积无定形金属氧化物介电层。在小于或等于400摄氏度的温度下用等离子体处理无定形金属氧化物介电层以形成结晶层。

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