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1. 发明授权

US06498522B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06498522B2
公开(公告)日：2002-12-24
申请号：US09833045
申请日：2001-04-12
申请人： Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
发明人： Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
IPC分类号： H03L700
CPC分类号： G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.
摘要翻译：本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。

2. 发明授权

US06185149B2 Semiconductor integrated circuit memory 有权
标题翻译：半导体集成电路存储器
公开(公告)号：US06185149B2
公开(公告)日：2001-02-06
申请号：US09340147
申请日：1999-06-28
申请人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
发明人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.
摘要翻译：半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块长度。从上述一个或多个存储单元块读取数据。

3. 发明授权

US06724675B2 Semiconductor memory device and electronic apparatus 有权
标题翻译：半导体存储器件和电子设备
公开(公告)号：US06724675B2
公开(公告)日：2004-04-20
申请号：US10352985
申请日：2003-01-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

4. 发明授权

US06535950B1 Semiconductor memory device having a refresh operation 有权
标题翻译：具有刷新操作的半导体存储器件
公开(公告)号：US06535950B1
公开(公告)日：2003-03-18
申请号：US09536988
申请日：2000-03-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C114093
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

5. 发明授权

US06427197B1 Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations 有权
标题翻译：半导体存储器件与时钟信号同步工作，用于高速数据写入和数据读取操作
公开(公告)号：US06427197B1
公开(公告)日：2002-07-30
申请号：US09394891
申请日：1999-09-13
申请人： Yasuharu Sato , Tadao Aikawa , Shinya Fujioka , Waichiro Fujieda , Hitoshi Ikeda , Hiroyuki Kobayashi
发明人： Yasuharu Sato , Tadao Aikawa , Shinya Fujioka , Waichiro Fujieda , Hitoshi Ikeda , Hiroyuki Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/1039
摘要： The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.
摘要翻译：本发明是一种存储电路，用于响应于写命令，写入根据突发长度确定的指定数量的写入数据，包括：第一级，用于与第一级同时输入，然后保持行地址和列地址写命令第二级具有经由流水线开关连接到第一级的存储器核，其中行地址和列地址被解码，字线和检测放大器被激活; 用于串行输入写入数据并且将写入数据并行地发送到存储器核心的第三级; 以及串行数据检测电路，用于在输入了规定数量的写入数据之后，产生用于使流水线开关导通的写入流水线控制信号。根据本发明，在呈现流水线结构的FCRAM中，可以在以突发长度安全地取出写入数据之后激活第二级中的存储器核心。此外，当连续写入或连续读取时，无论突发长度如何，命令循环可以变短。

6. 发明授权

US06721910B2 Semiconductor memory improved for testing 有权
标题翻译：半导体存储器改进了测试
公开(公告)号：US06721910B2
公开(公告)日：2004-04-13
申请号：US09400831
申请日：1999-09-21
申请人： Kazuhiro Ninomiya , Shinya Fujioka , Yasuharu Sato
发明人： Kazuhiro Ninomiya , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C2900
CPC分类号： G11C5/063 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： A synchronous DRAM (SDRAM) or a fast cycle RAM (FCRAM) includes capacitors connected by switches to a signal wire. The switches are controlled to connect and disconnect the capacitors to the signal wire. In a test mode, the transmission time of a control signal is tested by connecting various combinations of the capacitors to the signal wire, and then measuring the signal timing. The signal timing of the memory device can be controlled by selecting which and how many of the capacitors are connected to the signal wire.
摘要翻译：同步DRAM（SDRAM）或快速周期RAM（FCRAM）包括通过开关连接到信号线的电容器。控制开关将电容器连接到信号线。在测试模式下，通过将各种电容器的组合连接到信号线，然后测量信号时序来测试控制信号的传输时间。可以通过选择哪个和多少电容器连接到信号线来控制存储器件的信号定时。

7. 发明授权

US06459641B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06459641B2
公开(公告)日：2002-10-01
申请号：US09834945
申请日：2001-04-16
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
摘要翻译：本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元，生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

8. 发明授权

US06353561B1 Semiconductor integrated circuit and method for controlling the same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US06353561B1
公开(公告)日：2002-03-05
申请号：US09397845
申请日：1999-09-17
申请人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
发明人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.
摘要翻译：诸如同步DRAM的半导体存储器件经由输入缓冲器接收外部命令和外部时钟信号。该器件产生的频率低于外部时钟信号的内部时钟信号，并使用内部时钟信号来获取外部命令。这允许在外部时钟的每个周期获取多于一个外部命令。获取的外部命令被提供给命令解码器进行解码。当第一解码器电路解码外部命令时，掩码电路连接到解码器电路，并且禁止解码电路以外的第一解码电路在预定时间段内解码外部命令。

9. 发明授权

US06246620B1 Semiconductor memory device 有权
公开(公告)号：US06246620B1
公开(公告)日：2001-06-12
申请号：US09533759
申请日：2000-03-23
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

10. 发明授权

US6108243A High-speed random access memory device 有权
标题翻译：高速随机存取存储器
公开(公告)号：US6108243A
公开(公告)日：2000-08-22
申请号：US383014
申请日：1999-08-25
申请人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
发明人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1018 , G11C7/1039 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.
摘要翻译：本发明是一种FCRAM，包括用于执行命令解码的第一级，用于执行读出放大器激活的第二级，以及在流水线结构中执行数据输入和输出的第三级，并行传输的多个数据位在读出放大器和第三级之间，其中读出放大器被自动去激活，并且在数据已经在感测放大器和第三级之间并行传送之后，响应于标准的读或写命令来执行复位操作。

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