专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06721910B2 Semiconductor memory improved for testing 有权
标题翻译：半导体存储器改进了测试
公开(公告)号：US06721910B2
公开(公告)日：2004-04-13
申请号：US09400831
申请日：1999-09-21
申请人： Kazuhiro Ninomiya , Shinya Fujioka , Yasuharu Sato
发明人： Kazuhiro Ninomiya , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C2900
CPC分类号： G11C5/063 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： A synchronous DRAM (SDRAM) or a fast cycle RAM (FCRAM) includes capacitors connected by switches to a signal wire. The switches are controlled to connect and disconnect the capacitors to the signal wire. In a test mode, the transmission time of a control signal is tested by connecting various combinations of the capacitors to the signal wire, and then measuring the signal timing. The signal timing of the memory device can be controlled by selecting which and how many of the capacitors are connected to the signal wire.
摘要翻译：同步DRAM（SDRAM）或快速周期RAM（FCRAM）包括通过开关连接到信号线的电容器。控制开关将电容器连接到信号线。在测试模式下，通过将各种电容器的组合连接到信号线，然后测量信号时序来测试控制信号的传输时间。可以通过选择哪个和多少电容器连接到信号线来控制存储器件的信号定时。

2. 发明授权

US06427197B1 Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations 有权
标题翻译：半导体存储器件与时钟信号同步工作，用于高速数据写入和数据读取操作
公开(公告)号：US06427197B1
公开(公告)日：2002-07-30
申请号：US09394891
申请日：1999-09-13
申请人： Yasuharu Sato , Tadao Aikawa , Shinya Fujioka , Waichiro Fujieda , Hitoshi Ikeda , Hiroyuki Kobayashi
发明人： Yasuharu Sato , Tadao Aikawa , Shinya Fujioka , Waichiro Fujieda , Hitoshi Ikeda , Hiroyuki Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/1039
摘要： The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.
摘要翻译：本发明是一种存储电路，用于响应于写命令，写入根据突发长度确定的指定数量的写入数据，包括：第一级，用于与第一级同时输入，然后保持行地址和列地址写命令第二级具有经由流水线开关连接到第一级的存储器核，其中行地址和列地址被解码，字线和检测放大器被激活; 用于串行输入写入数据并且将写入数据并行地发送到存储器核心的第三级; 以及串行数据检测电路，用于在输入了规定数量的写入数据之后，产生用于使流水线开关导通的写入流水线控制信号。根据本发明，在呈现流水线结构的FCRAM中，可以在以突发长度安全地取出写入数据之后激活第二级中的存储器核心。此外，当连续写入或连续读取时，无论突发长度如何，命令循环可以变短。

3. 发明授权

US06333890B1 Memory device with a plurality of common data buses 有权
标题翻译：具有多个公共数据总线的存储器件
公开(公告)号：US06333890B1
公开(公告)日：2001-12-25
申请号：US09695302
申请日：2000-10-25
申请人： Masahiro Niimi , Shinya Fujioka , Tadao Aikawa , Yasuharu Sato
发明人： Masahiro Niimi , Shinya Fujioka , Tadao Aikawa , Yasuharu Sato
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C7/1069 , G11C7/18 , G11C8/12 , G11C2207/108
摘要： According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area. According to the present invention, there is provided a memory device having a plurality of banks each including a plurality of memory cells, and reading or writing data from or into the memory cells in synchronism with a clock signal, the memory device comprising: a sense amplifier disposed on each of the plurality of banks, for amplifying data read from the memory cells; a plurality of common data buses shared by the plurality of banks, the number of the common data buses being less than the number of the banks; and a switching circuit disposed on each of the plurality of banks, for feeding or receiving data of the each bank to or from the plurality of common data buses; wherein read or write of data of the plurality of banks is made through successive selection of the plurality of common data buses by the switching circuit.
摘要翻译：根据本发明的一个方面，具有多个存储体的存储器件通过使用多个公共数据总线执行存储体交织，该数据总线的数量少于存储体的数量。本发明能够在抑制芯片面积的增加的同时更快地读取数据。根据本发明，提供了一种具有多个存储单元的存储器件，每个存储单元包括多个存储器单元，以及与时钟信号同步地从存储器单元读取或写入数据，所述存储器件包括：感测放大器设置在所述多个存储体中的每一个上，用于放大从所述存储器单元读取的数据; 由所述多个银行共享的多个公用数据总线，所述公共数据总线的数量小于所述存储体的数量; 以及切换电路，其设置在所述多个存储体中的每一个上，用于向所述多个公共数据总线馈送或接收每个存储体的数据; 其中通过所述切换电路连续选择所述多个公用数据总线来进行所述多个存储体的数据的读取或写入。

4. 发明授权

US6026034A Bit line reset circuit of memory 失效
标题翻译：存储器的位线复位电路
公开(公告)号：US6026034A
公开(公告)日：2000-02-15
申请号：US73928
申请日：1998-05-07
申请人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
发明人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , G11C11/407 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4091 , G11C11/4094 , G11C7/12
摘要： Switching transistors 20, 22, 22P, 21, 23 and 23P and a portion of control circuit for transistors 20 and 21 constitutes a bit line reset circuit on memory cell side. In reading `H` from the memory cell connected to a bit line BLC or *BLC, the both bit lines are set at a higher reset potential Vii, while in reading `L`, the both bit lines are reset at a lower reset potential Vss. Transfer gates 10 and 11 are turned off before sufficient amplification of a potential difference between the bit lines BL and *BL. The operation of restoring into a memory cell read destructively from is performed in parallel with the operation of bit line reset.
摘要翻译：开关晶体管20,22,22P，21,23和23P以及用于晶体管20和21的控制电路的一部分构成存储单元侧的位线复位电路。在从连接到位线BLC或* BLC的存储单元读取“H”时，两个位线都被设置在较高的复位电位Vii，而在读取“L”时，两个位线都以较低的复位电位复位 Vss。在充分放大位线BL和* BL之间的电位差之前，转移门10和11被截止。与位线复位的操作并行执行从存储单元中恢复读取的操作。

5. 发明授权

US06459641B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06459641B2
公开(公告)日：2002-10-01
申请号：US09834945
申请日：2001-04-16
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
摘要翻译：本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元，生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

6. 发明授权

US06353561B1 Semiconductor integrated circuit and method for controlling the same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US06353561B1
公开(公告)日：2002-03-05
申请号：US09397845
申请日：1999-09-17
申请人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
发明人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.
摘要翻译：诸如同步DRAM的半导体存储器件经由输入缓冲器接收外部命令和外部时钟信号。该器件产生的频率低于外部时钟信号的内部时钟信号，并使用内部时钟信号来获取外部命令。这允许在外部时钟的每个周期获取多于一个外部命令。获取的外部命令被提供给命令解码器进行解码。当第一解码器电路解码外部命令时，掩码电路连接到解码器电路，并且禁止解码电路以外的第一解码电路在预定时间段内解码外部命令。

7. 发明授权

US06246620B1 Semiconductor memory device 有权
公开(公告)号：US06246620B1
公开(公告)日：2001-06-12
申请号：US09533759
申请日：2000-03-23
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

8. 发明授权

US6108243A High-speed random access memory device 有权
标题翻译：高速随机存取存储器
公开(公告)号：US6108243A
公开(公告)日：2000-08-22
申请号：US383014
申请日：1999-08-25
申请人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
发明人： Takaaki Suzuki , Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1018 , G11C7/1039 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.
摘要翻译：本发明是一种FCRAM，包括用于执行命令解码的第一级，用于执行读出放大器激活的第二级，以及在流水线结构中执行数据输入和输出的第三级，并行传输的多个数据位在读出放大器和第三级之间，其中读出放大器被自动去激活，并且在数据已经在感测放大器和第三级之间并行传送之后，响应于标准的读或写命令来执行复位操作。

9. 发明授权

US6088291A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6088291A
公开(公告)日：2000-07-11
申请号：US147600
申请日：1999-01-29
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/408 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C7/06 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
摘要翻译： PCT No.PCT / JP98 / 02443 Sec。 371日期1999年1月29日第 102（e）日期1999年1月29日PCT提交1998年6月3日PCT公布。第WO98 / 56004号公报日期：1998年12月10日本发明旨在提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元，生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

10. 发明授权

US06185149B2 Semiconductor integrated circuit memory 有权
标题翻译：半导体集成电路存储器
公开(公告)号：US06185149B2
公开(公告)日：2001-02-06
申请号：US09340147
申请日：1999-06-28
申请人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
发明人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.
摘要翻译：半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块长度。从上述一个或多个存储单元块读取数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式