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1. 发明专利

JPS59191196A Nonvolatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：JPS59191196A
公开(公告)日：1984-10-30
申请号：JP6533183
申请日：1983-04-15
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： NABEYA SHINJI , SATOU NOBUYUKI
IPC分类号： G11C16/02 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To emancipate a user from troubles of time control and to make the device easy to handle by realizing the proper time for writing or erasing in each memory cell without compelling the user to perform troublesome time control. CONSTITUTION:A pulse generating circuit 32 is started by a controlling signal i.e. a program signal Po given from the outside for writing or erasing, and generates a pulse signal Pi of specified time width. An MOS transistor of floating gate structure is used in each memory cell that constitutes a memory matrix 10. In the case of floating gate structure, writing of storage data is made by accumulation of charge in the gate. Erasing is made by discharging accumulated charges of the gate. Accumulation of charges of the gate or discharging of charges from the gate is made in a gate writing circuit 24 or an erasing circuit 26 by using the high voltage generated in a writing/erasing voltage generating circuit 28.
摘要翻译：目的：解决用户从时间控制的麻烦，通过在每个存储单元中实现写入或擦除的适当时间，使设备易于处理，而不需要用户执行麻烦的时间控制。构成：通过控制信号（即从外部给出的编程信号Po）进行写入或擦除来启动脉冲发生电路32，并产生规定时间宽度的脉冲信号Pi。在构成存储矩阵10的每个存储单元中使用浮置栅极结构的MOS晶体管。在浮栅结构的情况下，通过栅极中的电荷积累来进行存储数据的写入。通过放电门的累积电荷进行擦除。通过使用在写入/擦除电压产生电路28中产生的高电压，在栅极写入电路24或擦除电路26中进行栅极充电的积累或从栅极放电。

2. 发明专利

JPS59135698A Eeprom device 失效
标题翻译： EEPROM设备
公开(公告)号：JPS59135698A
公开(公告)日：1984-08-03
申请号：JP726683
申请日：1983-01-21
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： NABEYA SHINJI , SATOU NOBUYUKI
IPC分类号： G11C16/02 , G06K19/07 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To reduce a data rewrite time by erasing a data of a memory cell only when a data written newly is different from the data written already in the address location and writing a new data to save the time required for the write of data without change. CONSTITUTION:When an input data is coincident with a read data, no rewrite of data is executed and the time required for the erase and write is omitted. When the input data is not coincident with the read data, an output of a gate circuit 9 goes to a high level and an erase circuit 10 is operated. Then, the data in a memory cell corresponding to the address signal applied for the case is erased by 8-bits at the same time. Then, a write circuit 11 is operated by a pulse outputted from the erase circuit 10 at the end of data erase so that the new input data is written in the erased memory cell. Thus, the rewrite time reguired for the entire EEPROM device is reduced remarkably.
摘要翻译：目的：仅当新写入的数据与已写入地址位置的数据不同时，才能通过擦除存储单元的数据来减少数据重写时间，并写入新数据以节省数据写入所需的时间，而无需更改。构成：当输入数据与读取数据一致时，不执行数据重写，擦除和写入所需的时间被省略。当输入数据与读取数据不一致时，门电路9的输出变为高电平，擦除电路10运行。然后，与应用于该情况的地址信号相对应的存储单元中的数据同时被擦除8位。然后，在数据擦除结束时，由擦除电路10输出的脉冲对写入电路11进行操作，以便将新的输入数据写入被擦除的存储单元。因此，整个EEPROM器件所需的重写时间显着降低。

3. 发明专利

JPS5955071A Non-volatile semiconductor device 失效
标题翻译：非挥发性半导体器件
公开(公告)号：JPS5955071A
公开(公告)日：1984-03-29
申请号：JP16491082
申请日：1982-09-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： SATOU NOBUYUKI , UCHIUMI CHIKATAKE , NABEYA SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0433 , G11C16/0466 , H01L29/7883
摘要： PURPOSE: To increase the capacity of a memory and to simplify the memory circuit configuration by forming insulating films in a double strucure of insulating films of different dielectric constants under a floating gate, forming the thickness of the insulating film of upper layer in the prescribed value or lower, and disposing a charge collecting center in the floating gate.
CONSTITUTION: A field oxidized film 11 is formed on a P type substrate or a P type well 10 to form an element forming region, and an N
+ type regions 12, 13 which form source and drain regions are formed in the region. An SiO
2 film 14 having a thickness of approx. 20Å is formed on the surface of the element forming region, and an Si
3 N
4 film 15 having a thickness of approx. 60Å is formed at the position of the gate. A polysilicon is deposited on the film 15 to form a floating gate thereon. Further, an SiO
2 film 17 is formed a relatively thickly thereon, a polysilicon is deposited thereon to form a control gate 18. Aluminum wirings 20 are electrically connected through contacting holes 21a, 21b to N
+ type regions 12, 13.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了增加存储器的容量，并通过在浮置栅极下在不同介电常数的绝缘膜的双结构中形成绝缘膜来简化存储器电路配置，将上层绝缘膜的厚度设定在规定值或更低，并且在所述浮动门中设置电荷收集中心。构成：在P型基板或P型阱10上形成场氧化膜11，形成元件形成区域，在该区域形成形成源区和漏区的N +型区域12,13。具有厚度约为2μm的SiO 2膜14。 20A元件形成在元件形成区域的表面上，厚度约为3μm的Si 3 N 4膜15。 60A形成在门的位置。多晶硅沉积在膜15上以在其上形成浮栅。此外，SiO 2膜17在其上相对厚地形成，多晶硅沉积在其上以形成控制栅极18.铝布线20通过接触孔21a，21b电连接到N +型区域12,13。

4. 发明专利

JPS6124094A Memory device for semiconductor 失效
标题翻译：半导体存储器件
公开(公告)号：JPS6124094A
公开(公告)日：1986-02-01
申请号：JP14238084
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： UJIIE KAZUAKI , SATO NOBUYUKI , TERASAWA MASAAKI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE: To shorten a rewriting time of data in total by withdrawing a charge inputted by write-in voltage by higher voltage, and by making the length of an erasing time the same degree as that of a write-in time.
CONSTITUTION: A boosting circuit 8 consists of switches MOSFETs Q
1 , Q
2 connected in series with clamp diodes D
1 , D
2 to form a fixed write-in voltage Vpp
1 and an erasing voltage Vpp
2 controlling the voltage generated by charge pump 10 generating far higher voltage than electric source voltage Vcc, pushing up the level gradually receiving supply of charge from electric source voltage Vcc supplied from the outside. The voltage boosted by a charge pump 10 is clamped by break down voltage of clamp diode to generate the stabilized write-in voltage Vpp
1 and erasing voltage Vpp
2 . Thus, the time for rewriting all the data of EEPROM device will be largely shortened.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过以较高的电压撤销由写入电压输入的电荷，并使擦除时间的长度与写入时间相同的程度来缩短数据的重写时间。构成：升压电路8由与钳位二极管D1，D2串联连接的开关MOSFET Q1，Q2组成，以形成固定的写入电压Vpp1，以及擦除电压Vpp2，其控制由电荷泵10产生的电压远高于电压源极电压Vcc，从外部提供的电源电压Vcc向上推动逐渐接收电荷的电平。由电荷泵10升压的电压被钳位二极管的分压钳位，以产生稳定的写入电压Vpp1和擦除电压Vpp2。因此，重写EEPROM设备的所有数据的时间将大大缩短。

5. 发明专利

JPS63239692A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63239692A
公开(公告)日：1988-10-05
申请号：JP7150587
申请日：1987-03-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MUKODA HIDEFUMI , TERASAWA MASAAKI , IKEDA TAISUKE , NAGAI YOSHIKAZU , SATO NOBUYUKI , FURUSAWA KAZUNORI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/02
摘要： PURPOSE:To shorten a time required for a reliability test relating to rapid rewriting or data holding characteristics at the time of system operation by controlling the supplying time of a rewriting voltage in response to control data set in a timer control means. CONSTITUTION:The titled device is provided with the timer control means TMCONT for programmably controlling the supplying time of rewriting voltages Vwr, Ver outputted from a rewrite control means WEC for supplying a voltage required for data rewriting to an electrically rewritable semiconductor non- volatile memory element based on control data stored in a prescribed semiconductor non-volatile memory element or control data supplied from the external through an exclusive pad not bonded by a wire. Since the supplying time of the rewriting voltages Vwr, Ver is controlled in response to the control data set in the timer control means TMCONT, the time of a reliability test relating to the rapid rewriting or data holding characteristics at the time of system operation can be shortened.

6. 发明专利

JPS62197999A EEPROM DEVICE 失效
公开(公告)号：JPS62197999A
公开(公告)日：1987-09-01
申请号：JP3920586
申请日：1986-02-26
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATO NOBUYUKI , UJIIE KAZUAKI , FURUSAWA KAZUNORI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To make an operation into high speed by switching the potential of a word line to which an MNOS is coupled to the high voltage of positive/ negative, according to a decode output signal. CONSTITUTION:In a write operation, when a control signal; the inverse of R/W goes to a low level temporarily, a MOSFET Q5 turns to an on-state, then outputting the high voltage like+12V in a high voltage terminal Vpp. Therefore, a MOSFET Q6 is made turn to an off-state, then the high voltage like +12V at the second word line W12, etc., being generated. Therefore, the high voltage like +12V functions between the gate of the MNOS coupled to the second word line W12 and the gate of a base board, and the write operation by the implantation of electric charge based on a tunnel phenomenon is performed.

7. 发明专利

JPS6177197A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS6177197A
公开(公告)日：1986-04-19
申请号：JP19662784
申请日：1984-09-21
申请人： Hitachi Ltd
发明人： TANIDA YUJI , HAGIWARA TAKAAKI , MINAMI SHINICHI , NABEYA SHINJI , UCHIDA KEN , FURUNO TAKESHI
IPC分类号： G11C17/18 , G11C16/02 , G11C16/04 , G11C17/00 , H01L27/10
摘要： PURPOSE: To obtain a memory cell requiring no enhancement type reading transistor by applying the gate bias of an MIS type transistor belonging to a non-selection word line in a direction in which the transistor is not conductive.
CONSTITUTION: Gates of memory elements M11, M12, M21, M22 are connected through word lines W1, W2 to a switch 10 and an X decoder 12. Sources of the respective memory elements are connected through bit lines B1, B2 to a switch 14, a drain is connected through a switch 11 controlled by a Y decoder 16 to an input and output circuit 18 during reading, and a well is connected through an S1 to a switch 20. In case of reading the memory elements M11, M12, a word line W1 is set at 3V, a word line W2 at -0V, B1, B2 at 3V, and S1 at -0V. In this manner, without receiving the influence of the memory elements belonging to the non-selecting word lines, the information of the memory element constituted with one element/bit can be read.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在晶体管不导电的方向上施加属于非选择字线的MIS型晶体管的栅极偏置来获得不需要增强型读取晶体管的存储单元。构成：存储元件M11，M12，M21，M22的栅极通过字线W1，W2连接到开关10和X解码器12.各存储元件的源通过位线B1，B2连接到开关14，在读取期间，通过由Y解码器16控制的开关11将漏极连接到输入和输出电路18，并且通过S1将开关连接到开关20.在读取存储元件M11，M12的情况下，线W1设定为3V，字线W2为-0V，B1，B2为3V，S1为-0V。以这种方式，在不接收属于非选择字线的存储元件的影响的情况下，可以读取由一个元件/位构成的存储元件的信息。

8. 发明专利

JPS60256999A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS60256999A
公开(公告)日：1985-12-18
申请号：JP11293884
申请日：1984-06-04
申请人： HITACHI LTD
发明人： FURUNO TAKESHI , TANIDA YUUJI , HAGIWARA TAKAAKI , YOSHIZAKI KAZUO , SUGIURA JIYUN , NABEYA SHINJI , FUKUDA MINORU
IPC分类号： G11C16/06 , G11C17/00
摘要： PURPOSE:To supply a comparatively low voltage without level loss by using a control signal of a switch MOSFET supplying a comparatively low voltage with a voltage formed by a boosting circuit. CONSTITUTION:A write high voltage VPP and a read comparatively low voltage VCC are fed respectively to drains of MOSFETQ35, Q36 of differential form. On the other hand, the voltage VCC is fed steadily by an MOSFET37 of diode connection to a gate of the MOSFETQ36 supplying the voltage VCC. Further, a boosted voltage of the voltage VCC formed by a boosting circuit VG is fed to the gate of the MOSFET. Moreover, a voltage of a boostrap capacitor C is given to the gate of the FET36. Thus, in reading data at the read just after write, that is, a write high voltage VPP is applied, the voltage VCC fed to an address decoder circuit or the like is applied without level loss.

9. 发明专利

JPS60152057A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60152057A
公开(公告)日：1985-08-10
申请号：JP721584
申请日：1984-01-20
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SATOU NOBUYUKI , TERASAWA MASAAKI , UCHIDA KEN , NABEYA SHINJI , HAGIWARA TAKAAKI , TANIDA YUUJI
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/06 , H01L29/788 , H01L29/792 , H01L29/866
摘要： PURPOSE:To obtain different reference voltage easily by constituting a semiconductor device as constant-voltage diodes having each different withstanding voltage by utilizing the different junction withstanding voltage of two kinds of diodes having junctions of different shapes manufactured through the same process. CONSTITUTION:With a diode D1, a junction between high concentration (N type and P type) regions can be formed to a beltlike section along a P type region 11 to a plane shape parallel with the surface of a substrate 1 while a junction between the high concentration (N type) region and a low concentration (P type) region can be formed to a section shallower than the junction between the high concentration regions to a plane shape parallel with the surface of the substrate 1. With a diode D2, a junction between high concentration (N type and P type) regions can be shaped to the section surrounding the side surface of a P region 12 while a junction between the high concentration (N type) region and a low concentration (P type) region can be formed on a plane parallel with the surface of the substrate 1 in a section deeper than the junction between high concentration. Breakdown voltage at a time when P-N junctions are reverse-biassed differs in the diodes D1 and D2.

10. 发明专利

JPS6047299A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6047299A
公开(公告)日：1985-03-14
申请号：JP15488283
申请日：1983-08-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAGIWARA TAKAAKI , TANIDA YUUJI , NABEYA SHINJI , TERASAWA MASAAKI , UJIIE KAZUSATO , SATOU NOBUYUKI
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
摘要： PURPOSE:To increase the number of rewriting times of a nonvolatile memory by providing a defect relieving means reading a content of a spare bit on a chip to relieve a defective bit. CONSTITUTION:If a defective bit is recognized from the result of comparison of a comparator 11, the process moves to the defect relieving process. That is, a control circuit 13 operates a defect relieve drive circuit 12. The circuit 12 is operated even by an external test signal 121. When the circuit 12 is operated, relieve information is written in the nonvolatile memory of the defect relieving circuit 10. The stored information is two; address of the defective bit and 1-bit storing the application of relieve. The address comparison system is used for the address storage system of the defective bit. A spare memory 2 is constituted as plural number or provided in the column direction. In selecting the spare memory 2, address inputs ADRA4-A10 are coincident with addresses ADR'a4-a10 stored in the defect relieve circuit 10 in the comparison circuit in Fig. 1, an output 104 goes to high level and the spare memory 2 is selected.

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