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1. 发明专利

JPH01166396A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01166396A
公开(公告)日：1989-06-30
申请号：JP32407687
申请日：1987-12-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO NOBUYUKI , NAGAI YOSHIKAZU , UJIIE KAZUAKI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/02
摘要： PURPOSE:To prevent the undesired rewriting of data by individually setting an operating mode to fetch the data into a data input latch and an operating mode to rewrite a non-volatile memory cell with the data which are fetched into a data input latch. CONSTITUTION:The operating mode, which can fetch the data into a data input latch DILAT, and the operating mode, which can rewrite a memory cell array MCA by the data to be fetched into the data input latch DILAT, are individually set. Namely, the operating mode, which fetches the data to be supplied from an external part into the data input latch DILAT, is set by the change of a write-enable signal WE to a low level basically. Accordingly, the operating mode, which rewrites the memory cell array MCA by the data to be held by the data input latch DILAT, is enabled only when a write signal WR is caused to be a high level. Thus, the undesired rewriting of the data due to a guiding noise can be prevented.

2. 发明专利

JPS63127495A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63127495A
公开(公告)日：1988-05-31
申请号：JP27186586
申请日：1986-11-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FURUNO TAKESHI , FURUSAWA KAZUNORI , SATO NOBUYUKI , UJIIE KAZUAKI , NAGAI YOSHIKAZU
IPC分类号： G11C17/00 , H03K3/03 , H03K5/13 , H03K5/133 , H03K5/134
摘要： PURPOSE:To stabilize an oscillation circuit utilizing an undermentioned circuit by constituting a signal delay circuit to be built-in in an IC with a resistance element and a capacitor, and increasing the fluctuation of a second resistance element against the process fluctuation of a first resistance element, and changing a current conducted into a second capacitor greatly. CONSTITUTION:Invertor circuits N1-N5, consisting of odd number being cascade-connected in a ring shape, and the delay circuit, installed between them, constitute an oscillation circuit. Namely, the delay circuit, installed between the output of the invertor circuit N1 and the input of the invertor circuit N2, is constituted with a time constant circuit consisting of the first resistor R1 and a first capacitor C1, and with a series circuit, parallel-connected with the capacitor C1 and consisting of a second resistor R2 and a second capacitor C2. At this time, the second resistor R2 ismade to have the large fluctuation than the process fluctuation of the R1, so that the change portion of a charging and discharging current, against the capacitor C1 and due to the change of the resistance value of the resistor R1, is compensated.

3. 发明专利

JPS6329397A EEPROM DEVICE 失效
公开(公告)号：JPS6329397A
公开(公告)日：1988-02-08
申请号：JP17165186
申请日：1986-07-23
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： SATO NOBUYUKI , NAGAI YOSHIKAZU , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To prevent the reduction in the level margin by switching a reference voltage fed to a differential type sense amplifier to a level according to a read signal level changed in response to number of times of writing to a memory cell. CONSTITUTION:A sense amplifier SA discriminates a high/low level for a read signal outputted to a common data line CD by the addressing of a memory array M-ARY while referencing the reference voltage of a voltage generating circuit. In case of lots of rewriting number of times to a MNOS transistor, a voltage generating circuit forming two reference voltages where a threshold voltage is shifted toward the high level is provided. One is used for a reference voltage forming when number of times of rewriting is comparatively less and the other is used to form a reference voltage when number of times of rewriting exceeds a prescribed number of times, and a switching signal S is supplied to a gate of a switch MOSFETQ17 corresponding to a column switch from the counter circuit. Thus, the reference voltage attended with the rewriting number of times is switched and the operating margin is improved and the desired data storage characteristic is obtained.

4. 发明专利

JPS62197998A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS62197998A
公开(公告)日：1987-09-01
申请号：JP3920486
申请日：1986-02-26
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATO NOBUYUKI , UJIIE KAZUAKI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To reduce a current consumption, and to suppress a noise to an another circuit, etc., by increasing a current supplying capacity in the start up time of a voltage generation circuit, and decreasing the current supplying capacity when an output voltage arrives at a prescribed voltage level. CONSTITUTION:When the voltage of a power source voltage Vpp is below than +25V, the output signal LVH of a level detection circuit LVC goes to a low level, therefore, the output of an inverter circuit N1 goes to a high level, and the output signal of frequency F in a ring oscillator circuit OSC is inputted to a voltage generation circuit VPG. At the voltage generation circuit VPG, the power source voltage Vpp having a comparatively large current consumption can be obtained. Meanwhile, when the voltage of the power source voltage Vpp arrives at +25V, the output signal LVH of the level detection circuit LVC goes to the high level, and the oscillation signal of frequency F/4 is inputted to the voltage generation circuit VPG. In this way, at the voltage generation circuit VPG, the power source voltage Vpp having a comparatively small current consumption can be obtained.

5. 发明专利

JPS62298096A EEPROM DEVICE 失效
公开(公告)号：JPS62298096A
公开(公告)日：1987-12-25
申请号：JP14012786
申请日：1986-06-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NABEYA SHINJI , SATO NOBUYUKI , NAGAI YOSHIKAZU
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06
摘要： PURPOSE:To set an optimum elimination and writing time in accordance with the process variance of a memory element by making variable a reference time which comes to be the reference of a deleting action and a writing action. CONSTITUTION:From NOR gate circuits G1-G5 to which reference frequencies F1-F4 frequency-divided by a frequency dividing circuit DV are supplied, a reference time signal F is outputted. The signal F is counted by a counter circuit CT and the output signal is supplied to a timing generating circuit TG. The generating circuit TG generates various types of the control signal in accordance with respective action modes. Here, by changing a frequency dividing ratio at the frequency dividing circuit DV, the reference time signal outputted from a counter circuit CT can be made variable. Consequently, the optimum deleting and writing time in accordance with the process variance of a memory element to form the memory array can be set.

6. 发明专利

JPS62220398A INTEGRATED CIRCUIT CARD 失效
公开(公告)号：JPS62220398A
公开(公告)日：1987-09-28
申请号：JP6411486
申请日：1986-03-24
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： UJIIE KAZUTOSHI , SATO NOBUYUKI , IKEDA TAISUKE , NABEYA SHINJI
IPC分类号： G06K19/07 , B42D15/02 , B42D15/10 , G06K19/00 , G06K19/077

7. 发明专利

JPH0312097A NONVOLATILE DRAM 失效
公开(公告)号：JPH0312097A
公开(公告)日：1991-01-21
申请号：JP14559889
申请日：1989-06-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NAGAI YOSHIKAZU , SATO NOBUYUKI , TSUYAMA TOMOSUKE , FURUSAWA KAZUNORI
IPC分类号： G11C14/00
摘要： PURPOSE:To make a circuit into a highly integrated circuit by using an NMOS transistor in a dynamic memory cell as a nonvolatile storage element instead of a static memory cell. CONSTITUTION:The NMOS transistor Q1 and a selective MOSFET Q1 are connected in series to the electrode on one side of the accumulative capacitance element Cs of a dynamic memory cell part. When data is rewritten, since a DRAM mode is set and a transfer mode can be set when information held with a memory cell is returned to the dynamic memory cell part of the memory cell prior to the DRAM mode, the data in the memory cell can be preserved when a power source is disconnected as keeping the same access speed as that of an ordinary DRAM between the outside. In such a way, by using the dynamic memory cell and using the NMOS transistor as the nonvolatile storage element, structure can be simplified.

8. 发明专利

JPS63239692A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63239692A
公开(公告)日：1988-10-05
申请号：JP7150587
申请日：1987-03-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MUKODA HIDEFUMI , TERASAWA MASAAKI , IKEDA TAISUKE , NAGAI YOSHIKAZU , SATO NOBUYUKI , FURUSAWA KAZUNORI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/02
摘要： PURPOSE:To shorten a time required for a reliability test relating to rapid rewriting or data holding characteristics at the time of system operation by controlling the supplying time of a rewriting voltage in response to control data set in a timer control means. CONSTITUTION:The titled device is provided with the timer control means TMCONT for programmably controlling the supplying time of rewriting voltages Vwr, Ver outputted from a rewrite control means WEC for supplying a voltage required for data rewriting to an electrically rewritable semiconductor non- volatile memory element based on control data stored in a prescribed semiconductor non-volatile memory element or control data supplied from the external through an exclusive pad not bonded by a wire. Since the supplying time of the rewriting voltages Vwr, Ver is controlled in response to the control data set in the timer control means TMCONT, the time of a reliability test relating to the rapid rewriting or data holding characteristics at the time of system operation can be shortened.

9. 发明专利

JPS62197999A EEPROM DEVICE 失效
公开(公告)号：JPS62197999A
公开(公告)日：1987-09-01
申请号：JP3920586
申请日：1986-02-26
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATO NOBUYUKI , UJIIE KAZUAKI , FURUSAWA KAZUNORI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To make an operation into high speed by switching the potential of a word line to which an MNOS is coupled to the high voltage of positive/ negative, according to a decode output signal. CONSTITUTION:In a write operation, when a control signal; the inverse of R/W goes to a low level temporarily, a MOSFET Q5 turns to an on-state, then outputting the high voltage like+12V in a high voltage terminal Vpp. Therefore, a MOSFET Q6 is made turn to an off-state, then the high voltage like +12V at the second word line W12, etc., being generated. Therefore, the high voltage like +12V functions between the gate of the MNOS coupled to the second word line W12 and the gate of a base board, and the write operation by the implantation of electric charge based on a tunnel phenomenon is performed.

10. 发明专利

JPS62165798A EEPROM DEVICE 失效
公开(公告)号：JPS62165798A
公开(公告)日：1987-07-22
申请号：JP646586
申请日：1986-01-17
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATO NOBUYUKI , UJIIE KAZUTOSHI , IKEDA TAISUKE , FURUSAWA KAZUNORI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06
摘要： PURPOSE:To speed up the read by providing a separation N-channel MOSFET to a data line so as to turn off at write operation. CONSTITUTION:Gates of separation MOSFETs Q3 or the like are connected in common to a control line to which a control voltage Vig is supplied, sources are used in common to constitute a common source line CS. The common source line CS is coupled to an output terminal of a common source line drive circuit DVR. The circuit DVR drives nearly to a power voltage VCC level to the line CS at erasure and the line CS is driven to a ground level nearly at the circuit at read operation. Thus, when a well WELL is brought into a power supply voltage VCC level at erasure, the forward bias of the junction between the electrode of the FET Q3 coupled to the line CS and the well WELL is prevented. Further, a current path required for the read is formed between the line CS and a ground point of the circuit. The MOSFETs Q7, Q8 are brought nearly into a low level close to zero voltage at the read and write.

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