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1. 发明专利

JPS5955071A Non-volatile semiconductor device 失效
标题翻译：非挥发性半导体器件
公开(公告)号：JPS5955071A
公开(公告)日：1984-03-29
申请号：JP16491082
申请日：1982-09-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： SATOU NOBUYUKI , UCHIUMI CHIKATAKE , NABEYA SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0433 , G11C16/0466 , H01L29/7883
摘要： PURPOSE: To increase the capacity of a memory and to simplify the memory circuit configuration by forming insulating films in a double strucure of insulating films of different dielectric constants under a floating gate, forming the thickness of the insulating film of upper layer in the prescribed value or lower, and disposing a charge collecting center in the floating gate.
CONSTITUTION: A field oxidized film 11 is formed on a P type substrate or a P type well 10 to form an element forming region, and an N
+ type regions 12, 13 which form source and drain regions are formed in the region. An SiO
2 film 14 having a thickness of approx. 20Å is formed on the surface of the element forming region, and an Si
3 N
4 film 15 having a thickness of approx. 60Å is formed at the position of the gate. A polysilicon is deposited on the film 15 to form a floating gate thereon. Further, an SiO
2 film 17 is formed a relatively thickly thereon, a polysilicon is deposited thereon to form a control gate 18. Aluminum wirings 20 are electrically connected through contacting holes 21a, 21b to N
+ type regions 12, 13.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了增加存储器的容量，并通过在浮置栅极下在不同介电常数的绝缘膜的双结构中形成绝缘膜来简化存储器电路配置，将上层绝缘膜的厚度设定在规定值或更低，并且在所述浮动门中设置电荷收集中心。构成：在P型基板或P型阱10上形成场氧化膜11，形成元件形成区域，在该区域形成形成源区和漏区的N +型区域12,13。具有厚度约为2μm的SiO 2膜14。 20A元件形成在元件形成区域的表面上，厚度约为3μm的Si 3 N 4膜15。 60A形成在门的位置。多晶硅沉积在膜15上以在其上形成浮栅。此外，SiO 2膜17在其上相对厚地形成，多晶硅沉积在其上以形成控制栅极18.铝布线20通过接触孔21a，21b电连接到N +型区域12,13。

2. 发明专利

GB2129611B A NONVOLATILE MEMORY 未知
公开(公告)号：GB2129611B
公开(公告)日：1986-07-16
申请号：GB8322568
申请日：1983-08-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATO NOBUYUKI , UCHIUMI KYOTAKE , NABETANI SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , H01L29/78 , H01L29/50

3. 发明专利

DE3334557A1 未知
公开(公告)号：DE3334557A1
公开(公告)日：1984-04-05
申请号：DE3334557
申请日：1983-09-23
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATO NOBUYUKI , UCHIUMI KYOTAKE , NABETANI SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , G11C17/04 , H01L21/314 , H01L27/00

4. 发明专利

MY8700796A A NON VOLATILE MEMORY 未知
公开(公告)号：MY8700796A
公开(公告)日：1987-12-31
申请号：MY8700796
申请日：1987-12-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATO NOBUYUKI , UCHIUMI KYOTAKE , NABETANI SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , H01L29/78 , H01L29/50

5. 发明专利

FR2533740A1 未知
公开(公告)号：FR2533740A1
公开(公告)日：1984-03-30
申请号：FR8312885
申请日：1983-08-04
申请人： HITACHI LTD
发明人： SATO NOBUYUKI , UCHIUMI KYOTAKE , NABETANI SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , G11C17/00

6. 发明专利

HK1688A A NONVOLATILE MEMORY 未知
公开(公告)号：HK1688A
公开(公告)日：1988-01-15
申请号：HK1688
申请日：1988-01-07
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATO NOBUYUKI , UCHIUMI KYOTAKE , NABETANI SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , H01L29/78 , H01L29/50

7. 发明专利

GB2129611A A NONVOLATILE MEMORY 未知
公开(公告)号：GB2129611A
公开(公告)日：1984-05-16
申请号：GB8322568
申请日：1983-08-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATO NOBUYUKI , UCHIUMI KYOTAKE , NABETANI SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , H01L29/78 , H01L29/50

8. 发明专利

IT8322984D0 未知
公开(公告)号：IT8322984D0
公开(公告)日：1983-09-23
申请号：IT2298483
申请日：1983-09-23
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATO NOBUYUKI , UCHIUMI KYOTAKE , NABETANI SHINJI , UCHIDA KEN
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , G11C

9. 发明专利

DE3103143A1 未知
公开(公告)号：DE3103143A1
公开(公告)日：1981-12-03
申请号：DE3103143
申请日：1981-01-30
申请人： HITACHI LTD
发明人： SUGIURA JUNE , KOSA YASUNOBU , KOMORI KAZUHIRO , UCHIDA KEN , SHIMIZU SHINJI
IPC分类号： H01L27/112 , G11C5/02 , G11C16/04 , G11C17/00 , H01L21/8246 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40 , G11C17/06 , H01L21/72 , H05K7/06
摘要： A semiconductor memory device includes a number of conductive layers for bit and selection lines alternately juxtaposed on the surface of a semiconductor substrate beneath a field insulating layer, with a number of MOS type memory cells arranged between the conductive layers for the bit and selection lines.

10. 发明专利

JPH01184956A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01184956A
公开(公告)日：1989-07-24
申请号：JP831888
申请日：1988-01-20
申请人： HITACHI LTD
发明人： TAKEDA TOSHIFUMI , MEGURO SATOSHI , UCHIDA KEN
IPC分类号： H01L21/336 , H01L29/78
摘要： PURPOSE:To contrive the improvement of an integration density in a peripheral circuit by a method wherein, after the gate electrode of a MISFET is formed, an impurity is ion-implanted at a high energy transmitting the gate electrode to control the threshold voltage of this MISFET. CONSTITUTION:A photoresist 10 of a prescribed form is formed and thereafter, boron, for example, is ion implanted on the conditions of 180keV and a dose of 8.0-10 /cm using this photoresist 10 as a a mask. The boron ion-implanted at a high energy in such a way is transmitted a gate electrode 5 and is distributed widely in the depth direction in a p-type well 2. By the ion-implantation of this boron, the threshold voltage of an n-channel MOSFET Q1 is set at the final target value. Moreover, the impurity concentration at a part, in which this boron is ion-implanted, in the well 2 is augmented. As a result, a spreading of depletion layers to the side of a source region 8 in the p-n junction between a drain region 9 at the time of application of a voltage to a drain of the MOSFET Q1 and the well 2 can be inhibited.

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