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1. 发明专利

JPS60152057A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60152057A
公开(公告)日：1985-08-10
申请号：JP721584
申请日：1984-01-20
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SATOU NOBUYUKI , TERASAWA MASAAKI , UCHIDA KEN , NABEYA SHINJI , HAGIWARA TAKAAKI , TANIDA YUUJI
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/06 , H01L29/788 , H01L29/792 , H01L29/866
摘要： PURPOSE:To obtain different reference voltage easily by constituting a semiconductor device as constant-voltage diodes having each different withstanding voltage by utilizing the different junction withstanding voltage of two kinds of diodes having junctions of different shapes manufactured through the same process. CONSTITUTION:With a diode D1, a junction between high concentration (N type and P type) regions can be formed to a beltlike section along a P type region 11 to a plane shape parallel with the surface of a substrate 1 while a junction between the high concentration (N type) region and a low concentration (P type) region can be formed to a section shallower than the junction between the high concentration regions to a plane shape parallel with the surface of the substrate 1. With a diode D2, a junction between high concentration (N type and P type) regions can be shaped to the section surrounding the side surface of a P region 12 while a junction between the high concentration (N type) region and a low concentration (P type) region can be formed on a plane parallel with the surface of the substrate 1 in a section deeper than the junction between high concentration. Breakdown voltage at a time when P-N junctions are reverse-biassed differs in the diodes D1 and D2.

2. 发明专利

JPS6047299A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6047299A
公开(公告)日：1985-03-14
申请号：JP15488283
申请日：1983-08-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAGIWARA TAKAAKI , TANIDA YUUJI , NABEYA SHINJI , TERASAWA MASAAKI , UJIIE KAZUSATO , SATOU NOBUYUKI
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
摘要： PURPOSE:To increase the number of rewriting times of a nonvolatile memory by providing a defect relieving means reading a content of a spare bit on a chip to relieve a defective bit. CONSTITUTION:If a defective bit is recognized from the result of comparison of a comparator 11, the process moves to the defect relieving process. That is, a control circuit 13 operates a defect relieve drive circuit 12. The circuit 12 is operated even by an external test signal 121. When the circuit 12 is operated, relieve information is written in the nonvolatile memory of the defect relieving circuit 10. The stored information is two; address of the defective bit and 1-bit storing the application of relieve. The address comparison system is used for the address storage system of the defective bit. A spare memory 2 is constituted as plural number or provided in the column direction. In selecting the spare memory 2, address inputs ADRA4-A10 are coincident with addresses ADR'a4-a10 stored in the defect relieve circuit 10 in the comparison circuit in Fig. 1, an output 104 goes to high level and the spare memory 2 is selected.

3. 发明专利

JPS60251598A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60251598A
公开(公告)日：1985-12-12
申请号：JP10462984
申请日：1984-05-25
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SATOU NOBUYUKI , UJIIE KAZUAKI , TERASAWA MASAAKI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/20 , G11C16/22 , G11C16/30 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent wrong writing and wrong erasure in power-on operation and to eliminate the need for an external additional circuit by stopping substantially the operation of a boosting circuit by using a means which stores one level on the power-on operation. CONSTITUTION:An oscillation circuit OSC outputs pulses phi which vary periodically between a low and a high level when powered on and inverters IV1 and IV2 generate complementary pulses phi and -phi, which are supplied to the boosting circuit VBST. Then, a high voltage VPP of 5VCC is obtained at a capacitor 5 according to the high level of the pulses phi and -phi. The output of an FF as a power-on detecting circuit is held automatically at the high level, then the control signal (c) from a voltage detecting circuit VLD is held at the low level to make the operation of the circuit VBST ineffective, so that the voltage VPP is not outputted any more.

4. 发明专利

JPS60201593A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS60201593A
公开(公告)日：1985-10-12
申请号：JP5610784
申请日：1984-03-26
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATOU NOBUYUKI , MATSUO AKINORI , NABEYA SHINJI
IPC分类号： G11C14/00 , G11C11/40
摘要： PURPOSE:To decrease the number of NMOS required for nonvolatile storage information by allowing the MNOS to hold only one storage information via a selection MOSFET in storage information of a static type memory cell using a high resistor means as an information storage means. CONSTITUTION:Gates and drains of drive MOSFETQ1, Q2 are connected mutually in crossing. Gates and drains of the MOSFETQ1, Q2 connected in common are connected respectively to complementary data lines D, D' via transmission gates MOSFETQ3, Q4. The gates of the transmission gates MOSFETQ3, Q4 are connected in common to a word line W. The drains and gates of the MOSFETQ1, Q2 connected in common by the cross connection are regarded as information holding terminals. Since a selection MOSFET and an NMOS transistor have only to be added to the static memory cell holding the information with a high resistance, the number of elements is decreased remarkably.

5. 发明专利

JPS60200567A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60200567A
公开(公告)日：1985-10-11
申请号：JP5610884
申请日：1984-03-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MUTOU TADASHI , SATOU NOBUYUKI
IPC分类号： G11C17/00 , G11C16/06 , H01L21/8246 , H01L21/8247 , H01L27/02 , H01L27/10 , H01L27/112 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent an element from damaging while obtaining a margin of output level by connecting a well region formed in the output MOSFET of a power source voltage side during the operation of an output buffer circuit with its output terminal side, and providing a switching controller connected with the ground potential of the circuit during the inoperation. CONSTITUTION:Output MOSFETQ120 and Q121 are connected in a push-pull state, and a read signal is transmitted from an input/output terminal I/O. Q123 are coupled between a P type well region formed with the Q120 and the terminal I/O, and between a well region and a circuit grounding potential. An internal write enable signal we formed by the controller is supplied to the gate of Q123, and a signal -we inverted by an inverter IV is supplied to the gate of the Q122 to allow the signal we to set the Q123 to ON during the writing operation of high level, and the Q122 to ON during the reading operation of low level. Thus, the well region and the terminal I/O are connected during the reading operation. On the other hand, the well region and the ground potential of the circuit are connected except the above operations.

6. 发明专利

JPS60161643A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60161643A
公开(公告)日：1985-08-23
申请号：JP1523684
申请日：1984-02-01
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SATOU NOBUYUKI , KAMEI TAKAO , FUJIMOTO MICHIO , TERASAWA MASAAKI , MATSUO AKINORI
IPC分类号： H01L23/12 , H01L23/28 , H01L23/495 , H01L23/50
摘要： PURPOSE:To realize high density mounting of a semiconductor device insuring high productivity by a method wherein the leads of a lead frame are bent, and the device is so constructed as to make the surfaces of a part of the leads thereof to be exposed in the condition nearly coinciding with the surface of a resin molded package. CONSTITUTION:Leads 4 are bent at nearly right angles in the neighborhood of a tab 6, and bent toward the outside at nearly right angles again as to be made in nearly parallel with the tab 6 in the neighborhood of dums 7, the parallel parts of the leads in the neighborhood of the tab 6 are made as to construct the inner parts 4a, the parallel parts in the neighborhood of the dums 7 are made as to construct the outer parts 4b, and the standing up parts of the middle thereof are made as to construct the rigid parts 4c respectively. A pellet 8 is bonded to the tab 6 on the surface on the opposite side from the bent direction of the leads 4, and the pellet 8 is connected electrically through bonding wires 9 to the inner parts 4a at the respective leads 4. A lead frame 2 having the construction mentioned above is unhermetically sealed according to a package 10 formed by resin molding.

7. 发明专利

JPS5998394A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS5998394A
公开(公告)日：1984-06-06
申请号：JP20613382
申请日：1982-11-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： UCHIDA KEN , SATOU NOBUYUKI
IPC分类号： G11C16/06 , G11C17/00
摘要： PURPOSE:To extend a readout level margin by constituting an information storage element of an MNOSFET and providing a reference voltage generating circuit comprising an MNOSFET in a readout circuit. CONSTITUTION:A memory matrix MA has the MNOSFET constituting the information storage element and a memory cell MS comprising an MOSFET for selecting address connected in series therewith. Further, a data output circuit DOB on a semiconductor region separated from a semiconductor region WELL on which the matrix MA is formed has a reference voltage generating circuit including a dummy MNOSFET formed similarly with the information storage element and a differential sensing amplifier receiving readout information from the matrix MA and the reference voltage. As a result, the readout level margin is increased.

8. 发明专利

JPS60200574A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS60200574A
公开(公告)日：1985-10-11
申请号：JP5610384
申请日：1984-03-26
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATOU NOBUYUKI , UJIIE KAZUSATO , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06 , G11C16/10 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To enable to apply a high voltage for writing or erasing a memory cell while maintaining fixedly a substrate potential constant by forming capacities connected alternately with the gates of MNOS elements and high voltage generators by a pair of MOSFET. CONSTITUTION:A peripheral circuit is formed of C-MOS logic circuits, a high voltage generator 26 for applying a voltage for writing or erasing to a MNOS element Qm of memory cell, a pair of MOSFETQ1, Q2 complementarily driven to be conducted at writing or erasing time, and a capacity C connected alternately with the gate G of the element Qm and the generator 27 by the MOSFETs Q1, Q2 are provided. Further, the output voltage -Vpp from the generator 26 is applied to between the well 12 and the gate G, and the one is connected with the ground potential or the power source potential -Vpp.

9. 发明专利

JPS59191196A Nonvolatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：JPS59191196A
公开(公告)日：1984-10-30
申请号：JP6533183
申请日：1983-04-15
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： NABEYA SHINJI , SATOU NOBUYUKI
IPC分类号： G11C16/02 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To emancipate a user from troubles of time control and to make the device easy to handle by realizing the proper time for writing or erasing in each memory cell without compelling the user to perform troublesome time control. CONSTITUTION:A pulse generating circuit 32 is started by a controlling signal i.e. a program signal Po given from the outside for writing or erasing, and generates a pulse signal Pi of specified time width. An MOS transistor of floating gate structure is used in each memory cell that constitutes a memory matrix 10. In the case of floating gate structure, writing of storage data is made by accumulation of charge in the gate. Erasing is made by discharging accumulated charges of the gate. Accumulation of charges of the gate or discharging of charges from the gate is made in a gate writing circuit 24 or an erasing circuit 26 by using the high voltage generated in a writing/erasing voltage generating circuit 28.
摘要翻译：目的：解决用户从时间控制的麻烦，通过在每个存储单元中实现写入或擦除的适当时间，使设备易于处理，而不需要用户执行麻烦的时间控制。构成：通过控制信号（即从外部给出的编程信号Po）进行写入或擦除来启动脉冲发生电路32，并产生规定时间宽度的脉冲信号Pi。在构成存储矩阵10的每个存储单元中使用浮置栅极结构的MOS晶体管。在浮栅结构的情况下，通过栅极中的电荷积累来进行存储数据的写入。通过放电门的累积电荷进行擦除。通过使用在写入/擦除电压产生电路28中产生的高电压，在栅极写入电路24或擦除电路26中进行栅极充电的积累或从栅极放电。

10. 发明专利

JPS56102457A GRINDING METHOD 失效
公开(公告)号：JPS56102457A
公开(公告)日：1981-08-15
申请号：JP16154079
申请日：1979-12-14
申请人： HITACHI LTD
发明人： KATAGIRI KANTAROU , NAKAMURA SETSUO , SATOU NOBUYUKI , TAMURA FUMIHIKO , NAKAMURA TAKASHI
IPC分类号： B24B1/00
摘要： PURPOSE:To eliminate the formation of burrs and flashes when grinding the assembly of bar-shaped or plate-shaped articles by coating the assembly with a coating material and grinding the end faces of it in this state. CONSTITUTION:The surface of a part 1, an assembly (lamination) of plate-shaped articles like a core is coated with a coating material 4. Next, the end surface of this part 1 is ground together with this coating material 4. At this time, as the coating material 4 is stuck tightly to the laminated part 1, the part 1 is not peeled off when ground and no burr or flash is not formed.

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