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1. 发明专利

JPS62169452A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62169452A
公开(公告)日：1987-07-25
申请号：JP1012386
申请日：1986-01-22
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： KOIKE JUNICHI , KOBAYASHI ISAO
IPC分类号： H01L23/28 , H01L23/31 , H01L25/04 , H01L25/18
摘要： PURPOSE:To prevent the destruction of a CCB connected part caused by silicon gel by a method wherein a spacer is placed between a mother chip and a child chip. CONSTITUTION:A spacer 3 is interposed between a mother chip 1 and a child chip 2. The child chip 2 is fixed to the mother chip 1 with its protruded electrodes 4 and 4. The spacer 3 is fixed to the mother chip 1 in advance using a silicon rubber bonding agent and the like. As a result, the quantity of the silicon gel 14 filled into the gap of the chips 1 and 2 can be reduced, the thermal stress generated by the thermal expansion of the gel can be reduced, and the effect inflicted to the connected part of these chips 1 and 2 can also be lessened, thereby enabling the title semiconductor device to prevent the damage on the connected part caused by thermal stress.

2. 发明专利

JPS5819941B2 失效
公开(公告)号：JPS5819941B2
公开(公告)日：1983-04-20
申请号：JP15338076
申请日：1976-12-22
申请人： HITACHI LTD
发明人： KOIKE JUNICHI , MYANAKA MOTOSHI
IPC分类号： F23N5/14

3. 发明专利

JPH0745675A SCREENING INSPECTION JIG 失效
公开(公告)号：JPH0745675A
公开(公告)日：1995-02-14
申请号：JP19100493
申请日：1993-08-02
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： ISOBE TERUO , KOIKE JUNICHI
IPC分类号： H01L21/66
摘要： PURPOSE:To provide a screening inspection technique by which screening inspections can be accurately accomplished without deforming the lead pins of semiconductor devices. CONSTITUTION:A screening inspection jig is provided with a jig substrate 3, multiple conductor patterns 4 arranged in corresponding to the lead pins 2 of a semiconductor device 1, conductor patterns 11 formed in corresponding to multiple contact pins 12 on the performance board of a desired screening inspection device, through conductors 13 which respectively connect the patterns 4 and 11 to each other, and a fixture 10 from which fixed terminals 10a are projected. The jig is also provided with pin indenters 8 and package indenters 7 respectively arranged corresponding to the outer end sections of the lead pins 2 and package 1a of the semiconductor device 1, guide holes in which positioning pins, etc., provided on the performance board P are put, fixed patterns 5 independent from the conductor patterns 4, solder 14 which joints the fixed terminals 10a of the fixture 10 to fixed patterns 5 on the jig substrate 3.

4. 发明专利

JPH05298961A 失效
公开(公告)号：JPH05298961A
公开(公告)日：1993-11-12
申请号：JP10150092
申请日：1992-04-22
申请人： HITACHI LTD
发明人： MAKINO SATOSHI , KOIKE JUNICHI
IPC分类号： H01H13/70 , H01L23/36 , H01L23/40 , H05K7/20
摘要： PURPOSE:To improve the heat radiation efficiency of a portable electronic computer. CONSTITUTION:The portable electronic computer is constructed so that heat generated at a semiconductor integrated circuit housed in the equipment body 2b in a note-type personal computer 1a may eascape from the key top 4a and the key base of a key input 4. A fin 4a1 is formed at the side of the key top 4a, and also the key top 4a and the key base 4b are made up of metal whose coefficient of thermal conductivity is high.

5. 发明专利

JPS63164349A OUTER LEAD PIN FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63164349A
公开(公告)日：1988-07-07
申请号：JP30850686
申请日：1986-12-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOIKE JUNICHI , TSUBOI TOSHIHIRO
IPC分类号： H01L23/12 , H01L23/50 , H05K3/30 , H05K3/40
摘要： PURPOSE:To eliminate the need for the increase of the overall size of a package even when the number of signal pins augments by insulating a plurality of signal pins consisting of a conductor material and using the signal pins as one outer lead pin. CONSTITUTION:Two faced conductor sections 3, 3' are solidified by an insulator 4, and changed into one pin 2. The conductor sections 3 are constituted of a substance such as metal, and the pin 2 organized of the insulator 4 such as resin is acquired by disposing that two metal bars oppositely at a proper interval and disposed previously into a die such as a molding die, and by injecting the resin into the molding die. One conductor section 3 of the multiple pin 2 is connected to a wiring 13 for a substrate 12 for mounting by solder 14, and the other conductor section 3' of the multiple pin 2 is connected to a wiring 13' for the substrate 12 for mounting by solder 14'. Even when the number of the pins is doubled, only pins of the same number can be used, and the size of a package can be miniaturized, thus allowing high packaging density on mounting.

6. 发明专利

JPS61152054A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61152054A
公开(公告)日：1986-07-10
申请号：JP27281884
申请日：1984-12-26
申请人： HITACHI LTD
发明人： MURATA JUN , KOIKE JUNICHI , FUJITA MINORU
IPC分类号： H01L27/00 , H01L21/768 , H01L21/8238 , H01L27/06 , H01L27/092
摘要： PURPOSE:To establish an ohmic contact without enhancing the concentration of impurities in N type and P type semiconductor regions by a method wherein a high-melting point metal silicide layer is formed between the semiconductor regions of two MISFET elements of different conductivity types in a complementary three-dimensional MISFET device. CONSTITUTION:On the primary surface of a substrate 1, element activation regions are formed, surrounded by a relatively thick SiO2 film serving as a field insulating layer, and N-channel MOSFETs are built in the element activation regions. In the diffusion layers of the source 3 and drain 4 of the N-channel MOSFETs, high-melting point metal silicide layers 5 are formed, respectively. The N-channel MOSFETs are isolated from P-channel MOSFETs by insulating films 8. The insulating films 8 also serve as gate insulating films for the P- channel MOSFETs and are locally provided with holes wherein ohmic contact is established between P-channel MOSFET drain regions 10 and N-channel MOSFET source regions 3 with the intermediary of the high-melting point meal silicide layers 5.

7. 发明专利

JPS6031106B2 失效
公开(公告)号：JPS6031106B2
公开(公告)日：1985-07-20
申请号：JP13406976
申请日：1976-11-10
申请人： HITACHI LTD
发明人： MASUDA HIROO , ETO JUN , KOYANAGI MITSUMASA , KOIKE JUNICHI
IPC分类号： H01L27/04 , H01L21/822

8. 发明专利

JPS628548A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS628548A
公开(公告)日：1987-01-16
申请号：JP14651685
申请日：1985-07-05
申请人： HITACHI LTD
发明人： KOIKE JUNICHI , FUJITA MINORU , MURATA JUN
IPC分类号： H01L27/00
摘要： PURPOSE:To flatten the upper surface of a second MISFET, by embedding the source region and the drain region of the second MISFET in a recess part having a step shape in a first MISFET. CONSTITUTION:On a substrate 1, a field insulating film 2, a channel stopper region 3, a gate insulating film 4, a gate electrode 5 and a semiconductor region 6 are formed. Thus an MISFET Qn is formed. Then, on the region 6, a conductor layer 7 and an insulating film 8 are formed. After a gate insulating film 9 is formed, a connecting hole 8A is formed. Then, a silicon film 10A and an irregularity absorbing layer 14 are formed in order to form a p-channel MISFET. Thus, the film 10A is embedded in the recess part of the region 6. Then, impurities are introduced in a single crystal silicon film 10, and an MISFET Tp is formed. Then, an insulating film 12, a connecting hole 12A and a conducting layer 13 are formed.

9. 发明专利

JPS61150252A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61150252A
公开(公告)日：1986-07-08
申请号：JP27086084
申请日：1984-12-24
申请人： HITACHI LTD
发明人： KOIKE JUNICHI , TAKEDA KATSUMI , SAGARA KAZUYOSHI
IPC分类号： H01L23/50 , H01L23/498 , H05K3/30 , H05K3/34
摘要： PURPOSE:To enable electrical connection of high reliability by a method wherein a cut is formed in the side surface of a lead pin in the longitudinal direction, and lead pins are fixed to a package substrate by pressure-welding the side surfaces of lead pins to through-hole walls under outer stress. CONSTITUTION:A lead pin 4 used for the titled device 1 has a large-diameter head 4b at one end of the pin main body 4a of small-diameter bar form and is provided with a cut 4c tapered toward the axis in the longitudinal direction of the side surface of the pin main body 4a. The pin 4 is inserted into a through- hole 13 which is much smaller in diameter than the main body of the pin 4 formed to the package substrate 2 and formed by extension of a wiring 3 on the wall while the pin main body 4a is pressed in the axial direction with a fixing tool, and is fixed to the substrate 2 by the pressure-welding of the side surface of the pin main body 4a to the through-hole wall 13 by release of said pressing after insertion. Besides, a solder 14 is risen on the wiring 3 around the projection of a lead pin 4 at the aperture part; thereby, the planting of lead pins 4 can be attained without damaging the wiring 3.

10. 发明专利

JPS61105873A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61105873A
公开(公告)日：1986-05-23
申请号：JP22005985
申请日：1985-10-04
申请人： Hitachi Ltd
发明人： KAMIGAKI YOSHIAKI , ITO KIYOO , ONISHI SHINJI , YOSHIDA ISAO , MASUDA HIROO , KOIKE JUNICHI
IPC分类号： H01L21/265 , H01L29/78
CPC分类号： H01L29/78
摘要： PURPOSE:To obtain a semiconductor device in a high-withstand voltage structure by a method wherein the high-concentration impurity region constituting the drain region is formed by the mask away from the gate electrode compared to the low= concentration impurity region. CONSTITUTION:An oxide film is formed on a substrate 1 by performing a thermal oxidation and after a 4,000-Angstrom thick polycrystalline silicon layer, wherein phosphorus is contained in high concentration, is desposited thereon, a gate insulating film 3 and a gate electrode 4 are formed. After that, a thermal oxidation is performed and phosphorus is ion-implanted in the substrate 1 as wide as 2X10 cm through oxide films 8-1 and 8-2, which are formed at the time of the foregoing thermal oxidation, and ion-implanted layers 5-1 and 5-2 are formed. Subsequently, wet and dry thermal oxidation are performed and 210-Angstrom thick oxide films 6-1 and 6-3 are formed on the substrate. At this time, a 3,000-Angstrom thick oxide film 6-2 is formed on the periphery of the electrode 4, because an impurity, phosphorus, is being contained in the polycrystalline silicon layer in high concentration. After then, arsenic is ion-implanted as wide as 6mu10 cm . After that, a thermal treatment is performed and phosphorus impurity layers 5-1 and 5-2 and arsenic impurity layers 7-1 and 7-2 are formed as the final diffusion layers.
摘要翻译：目的：为了通过以下方法获得高耐压结构的半导体器件：与低浓度杂质区相比，构成漏极区的高浓度杂质区由掩模形成，远离栅电极。构成：通过进行热氧化在基板1上形成氧化膜，在其上分布有高浓度磷的4,000埃厚的多晶硅层之后，栅极绝缘膜3和栅电极4为形成。之后，通过在上述时刻形成的氧化膜8-1和8-2，进行热氧化，并将磷离子注入到宽度为2×10 13 cm -2的衬底1中形成热氧化和离子注入层5-1和5-2。随后，进行湿干和干热氧化，并在衬底上形成210埃厚的氧化膜6-1和6-3。此时，由于在多晶硅层中含有高浓度的杂质，因此在电极4的周围形成有3,000埃厚的氧化膜6-2。之后，将砷离子注入到6mu10·15cm -2以上。之后，进行热处理，并且形成磷杂质层5-1和5-2以及砷杂质层7-1和7-2作为最终扩散层。

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