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1. 发明专利

JPS63164349A OUTER LEAD PIN FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63164349A
公开(公告)日：1988-07-07
申请号：JP30850686
申请日：1986-12-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOIKE JUNICHI , TSUBOI TOSHIHIRO
IPC分类号： H01L23/12 , H01L23/50 , H05K3/30 , H05K3/40
摘要： PURPOSE:To eliminate the need for the increase of the overall size of a package even when the number of signal pins augments by insulating a plurality of signal pins consisting of a conductor material and using the signal pins as one outer lead pin. CONSTITUTION:Two faced conductor sections 3, 3' are solidified by an insulator 4, and changed into one pin 2. The conductor sections 3 are constituted of a substance such as metal, and the pin 2 organized of the insulator 4 such as resin is acquired by disposing that two metal bars oppositely at a proper interval and disposed previously into a die such as a molding die, and by injecting the resin into the molding die. One conductor section 3 of the multiple pin 2 is connected to a wiring 13 for a substrate 12 for mounting by solder 14, and the other conductor section 3' of the multiple pin 2 is connected to a wiring 13' for the substrate 12 for mounting by solder 14'. Even when the number of the pins is doubled, only pins of the same number can be used, and the size of a package can be miniaturized, thus allowing high packaging density on mounting.

2. 发明专利

JPS61212050A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61212050A
公开(公告)日：1986-09-20
申请号：JP5231285
申请日：1985-03-18
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： SHOJI TAKASHI , KOIKE JUNICHI
IPC分类号： H01L21/60 , H01L23/485
摘要： PURPOSE:To enable to attain a highly reliable wire-bonding by a method wherein bonding pad groups, in each of which the bonding pads are formed at a slope in the directions of the inner end parts of the mutually corresponding leads, are respectively formed along each side of the pellet and the terminal bonding pad of each bonding pad group is formed in a configuration wider than the other bonding pads. CONSTITUTION:The bonding pads 5 of a pellet 2 are connected with the inner end parts of leads 3 corresponding to the bonding pads using wires 4. The bonding pads 5 are respectively formed on the pellet 2 in a square form and each of the square bonding pads 5 is formed at the prescribed slope in the direction of the inner end part of the mutually corresponding lead 3. The terminal bonding pad 5a of each of the bonding pad groups is formed wider in the rectangular direction to the inclining direction of the pads compared to the other bonding pads of the bonding pad group. By this way, an ultrasonic bonding can be attained with a sufficient margin.

3. 发明专利

JPS6224645A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6224645A
公开(公告)日：1987-02-02
申请号：JP16195785
申请日：1985-07-24
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： SHOJI TAKASHI , KOIKE JUNICHI
IPC分类号： H01L23/04 , H01L23/32 , H01L23/495 , H01L23/50 , H01L23/544 , H01R33/76
摘要： PURPOSE:To prevent the reverse insertion at the time of mounting a substrate by a method wherein recesses or projection sections that fit in the recess or projection sections formed on a mounting substrate to indicate the mounting direction are formed on a package. CONSTITUTION:A dummy lead 5a is attached on the one side of a package with a lead 5. The dummy lead 5a is horizontally extended from the one side of the package and bent in the middle section. In corresponding to the lead 5, a socket hole 10 is arranged on a socket 9 into which a semiconductor device 1 with such lead construction is to be mounted. A hole 10c for the dummy lead is opened on the socket hole line 10a on the a-line side, with larger number of holes than that of the b-line 10a only by one hole. Thus, when the semiconductor device 1 is to be mounted on the socket 9, the semiconductor device 1 must be mounted so that the lead side with a dummy lead 5a is placed on the side of the socket hole line 10a. By this method, it is made possible to easily recognize the accurate mounting direction and to prevent the reverse insertion at the time of mounting a substrate.

4. 发明专利

JPS62169452A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62169452A
公开(公告)日：1987-07-25
申请号：JP1012386
申请日：1986-01-22
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： KOIKE JUNICHI , KOBAYASHI ISAO
IPC分类号： H01L23/28 , H01L23/31 , H01L25/04 , H01L25/18
摘要： PURPOSE:To prevent the destruction of a CCB connected part caused by silicon gel by a method wherein a spacer is placed between a mother chip and a child chip. CONSTITUTION:A spacer 3 is interposed between a mother chip 1 and a child chip 2. The child chip 2 is fixed to the mother chip 1 with its protruded electrodes 4 and 4. The spacer 3 is fixed to the mother chip 1 in advance using a silicon rubber bonding agent and the like. As a result, the quantity of the silicon gel 14 filled into the gap of the chips 1 and 2 can be reduced, the thermal stress generated by the thermal expansion of the gel can be reduced, and the effect inflicted to the connected part of these chips 1 and 2 can also be lessened, thereby enabling the title semiconductor device to prevent the damage on the connected part caused by thermal stress.

5. 发明专利

JPS5819941B2 失效
公开(公告)号：JPS5819941B2
公开(公告)日：1983-04-20
申请号：JP15338076
申请日：1976-12-22
申请人： HITACHI LTD
发明人： KOIKE JUNICHI , MYANAKA MOTOSHI
IPC分类号： F23N5/14

6. 发明专利

JPH0745675A SCREENING INSPECTION JIG 失效
公开(公告)号：JPH0745675A
公开(公告)日：1995-02-14
申请号：JP19100493
申请日：1993-08-02
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： ISOBE TERUO , KOIKE JUNICHI
IPC分类号： H01L21/66
摘要： PURPOSE:To provide a screening inspection technique by which screening inspections can be accurately accomplished without deforming the lead pins of semiconductor devices. CONSTITUTION:A screening inspection jig is provided with a jig substrate 3, multiple conductor patterns 4 arranged in corresponding to the lead pins 2 of a semiconductor device 1, conductor patterns 11 formed in corresponding to multiple contact pins 12 on the performance board of a desired screening inspection device, through conductors 13 which respectively connect the patterns 4 and 11 to each other, and a fixture 10 from which fixed terminals 10a are projected. The jig is also provided with pin indenters 8 and package indenters 7 respectively arranged corresponding to the outer end sections of the lead pins 2 and package 1a of the semiconductor device 1, guide holes in which positioning pins, etc., provided on the performance board P are put, fixed patterns 5 independent from the conductor patterns 4, solder 14 which joints the fixed terminals 10a of the fixture 10 to fixed patterns 5 on the jig substrate 3.

7. 发明专利

JPH05298961A 失效
公开(公告)号：JPH05298961A
公开(公告)日：1993-11-12
申请号：JP10150092
申请日：1992-04-22
申请人： HITACHI LTD
发明人： MAKINO SATOSHI , KOIKE JUNICHI
IPC分类号： H01H13/70 , H01L23/36 , H01L23/40 , H05K7/20
摘要： PURPOSE:To improve the heat radiation efficiency of a portable electronic computer. CONSTITUTION:The portable electronic computer is constructed so that heat generated at a semiconductor integrated circuit housed in the equipment body 2b in a note-type personal computer 1a may eascape from the key top 4a and the key base of a key input 4. A fin 4a1 is formed at the side of the key top 4a, and also the key top 4a and the key base 4b are made up of metal whose coefficient of thermal conductivity is high.

8. 发明专利

JPS61152054A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61152054A
公开(公告)日：1986-07-10
申请号：JP27281884
申请日：1984-12-26
申请人： HITACHI LTD
发明人： MURATA JUN , KOIKE JUNICHI , FUJITA MINORU
IPC分类号： H01L27/00 , H01L21/768 , H01L21/8238 , H01L27/06 , H01L27/092
摘要： PURPOSE:To establish an ohmic contact without enhancing the concentration of impurities in N type and P type semiconductor regions by a method wherein a high-melting point metal silicide layer is formed between the semiconductor regions of two MISFET elements of different conductivity types in a complementary three-dimensional MISFET device. CONSTITUTION:On the primary surface of a substrate 1, element activation regions are formed, surrounded by a relatively thick SiO2 film serving as a field insulating layer, and N-channel MOSFETs are built in the element activation regions. In the diffusion layers of the source 3 and drain 4 of the N-channel MOSFETs, high-melting point metal silicide layers 5 are formed, respectively. The N-channel MOSFETs are isolated from P-channel MOSFETs by insulating films 8. The insulating films 8 also serve as gate insulating films for the P- channel MOSFETs and are locally provided with holes wherein ohmic contact is established between P-channel MOSFET drain regions 10 and N-channel MOSFET source regions 3 with the intermediary of the high-melting point meal silicide layers 5.

9. 发明专利

JPS6031106B2 失效
公开(公告)号：JPS6031106B2
公开(公告)日：1985-07-20
申请号：JP13406976
申请日：1976-11-10
申请人： HITACHI LTD
发明人： MASUDA HIROO , ETO JUN , KOYANAGI MITSUMASA , KOIKE JUNICHI
IPC分类号： H01L27/04 , H01L21/822

10. 发明专利

JPS628548A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS628548A
公开(公告)日：1987-01-16
申请号：JP14651685
申请日：1985-07-05
申请人： HITACHI LTD
发明人： KOIKE JUNICHI , FUJITA MINORU , MURATA JUN
IPC分类号： H01L27/00
摘要： PURPOSE:To flatten the upper surface of a second MISFET, by embedding the source region and the drain region of the second MISFET in a recess part having a step shape in a first MISFET. CONSTITUTION:On a substrate 1, a field insulating film 2, a channel stopper region 3, a gate insulating film 4, a gate electrode 5 and a semiconductor region 6 are formed. Thus an MISFET Qn is formed. Then, on the region 6, a conductor layer 7 and an insulating film 8 are formed. After a gate insulating film 9 is formed, a connecting hole 8A is formed. Then, a silicon film 10A and an irregularity absorbing layer 14 are formed in order to form a p-channel MISFET. Thus, the film 10A is embedded in the recess part of the region 6. Then, impurities are introduced in a single crystal silicon film 10, and an MISFET Tp is formed. Then, an insulating film 12, a connecting hole 12A and a conducting layer 13 are formed.

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