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1. 发明授权

US5405800A Method of fabricating a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US5405800A
公开(公告)日：1995-04-11
申请号：US274048
申请日：1994-07-12
申请人： Hisashi Ogawa , Susumu Matsumoto , Shin Hashimoto , Hiroyuki Umimoto
发明人： Hisashi Ogawa , Susumu Matsumoto , Shin Hashimoto , Hiroyuki Umimoto
IPC分类号： H01L27/108 , H01L21/70
CPC分类号： H01L27/10808
摘要： A method of fabricating a semiconductor memory device on a semiconductor substrate is disclosed. A gate electrode that becomes a word line, a bit line, and a charge-storage electrode are formed in a memory cell array region of a semiconductor substrate. A capacitor insulator layer and a plate electrode are formed in that order. Then, a BPSG film is formed in the memory cell array region and in the peripheral circuit region. A resist pattern is formed on the BPSG film, leaving the memory cell array region exposed. Using the resist pattern thus formed as a mask, an etching treatment is applied to remove an upper surface portion of the BPSG film lying within the memory cell array region by a given amount. After the resist pattern is removed, the BPSG film is heated in order that it reflows to planarize.
摘要翻译：公开了一种在半导体衬底上制造半导体存储器件的方法。在半导体衬底的存储单元阵列区域中形成成为字线，位线和电荷存储电极的栅电极。依次形成电容器绝缘体层和平板电极。然后，在存储单元阵列区域和外围电路区域中形成BPSG膜。在BPSG膜上形成抗蚀剂图案，使存储单元阵列区域暴露。使用如此形成的抗蚀剂图案作为掩模，进行蚀刻处理以将存在于存储单元阵列区域内的BPSG膜的上表面部分除去给定量。在除去抗蚀剂图案之后，加热BPSG膜，使其回流平坦化。

2. 发明授权

US5455205A Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5455205A
公开(公告)日：1995-10-03
申请号：US34763
申请日：1993-03-19
申请人： Hiroyuki Umimoto , Shin Hashimoto , Shinji Odanaka
发明人： Hiroyuki Umimoto , Shin Hashimoto , Shinji Odanaka
IPC分类号： H01L21/3105 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/02
CPC分类号： H01L27/10852 , H01L21/3105 , H01L27/108 , H01L27/105 , Y10S148/133 , Y10S438/978
摘要： There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film. With this construction, a step of the aluminum wiring in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is decreased, thereby preventing the lowering of the yield of the aluminum wiring which is caused by the cutting of the aluminum wiring and the remaining of a residue of etching for a contact-forming electrode (for example, tungsten).
摘要翻译：公开了一种制造半导体存储器件的方法。在包括开关晶体管的半导体衬底上形成层间绝缘膜。然后，形成到达开关晶体管的有源区的存储器节点图形。通过形成在存储节点上的绝缘膜形成单元板电极图案，使得通过从存储器节点图案和单元的重叠尺寸减去用于单元板电极的多晶硅膜的厚度而获得的值平板电极图案不小于BPSG膜的沉积厚度的两倍以上且不大于十倍。然后，将BPSG膜沉积在整个表面上，然后通过热处理使其粘稠流动。然后，在BPSG膜上形成铝布线。利用这种结构，在存储单元阵列部分和外围电路部分之间或字线 - 背衬接触形成区域中的边界区域中的铝布线的步骤减小，从而防止铝的收率降低通过切割铝布线引起的布线和剩余的用于接触形成电极（例如钨）的蚀刻残留物。

3. 发明授权

US5584964A Method of producing semiconductor device with viscous flow of silicon oxide 失效
标题翻译：生产氧化硅粘性流动半导体器件的方法
公开(公告)号：US5584964A
公开(公告)日：1996-12-17
申请号：US453806
申请日：1995-05-30
申请人： Hiroyuki Umimoto , Shin Hashimoto , Shinji Odanaka
发明人： Hiroyuki Umimoto , Shin Hashimoto , Shinji Odanaka
IPC分类号： H01L21/3105 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10852 , H01L21/3105 , H01L27/108 , H01L27/105 , Y10S148/133 , Y10S438/978
摘要： There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film. With this construction, a step of the aluminum wiring in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is decreased, thereby preventing the lowering of the yield of the aluminum wiring which is caused by the cutting of the aluminum wiring and the remaining of a residue of etching for a contact-forming electrode (for example, tungsten).
摘要翻译：公开了一种制造半导体存储器件的方法。在包括开关晶体管的半导体衬底上形成层间绝缘膜。然后，形成到达开关晶体管的有源区的存储器节点图形。通过形成在存储节点上的绝缘膜形成单元板电极图案，使得通过从存储器节点图案和单元的重叠尺寸减去用于单元板电极的多晶硅膜的厚度而获得的值平板电极图案不小于BPSG膜的沉积厚度的两倍以上且不大于十倍。然后，将BPSG膜沉积在整个表面上，然后通过热处理使其粘稠流动。然后，在BPSG膜上形成铝布线。利用这种结构，在存储单元阵列部分和外围电路部分之间或字线 - 背衬接触形成区域中的边界区域中的铝布线的步骤减小，从而防止铝的收率降低通过切割铝布线引起的布线和剩余的用于接触形成电极（例如钨）的蚀刻残留物。

4. 发明授权

US06995415B2 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06995415B2
公开(公告)日：2006-02-07
申请号：US10475115
申请日：2003-02-14
申请人： Hisashi Ogawa , Hiroaki Nakaoka , Atsuhiro Kajiya , Shin Hashimoto , Kyoko Egashira
发明人： Hisashi Ogawa , Hiroaki Nakaoka , Atsuhiro Kajiya , Shin Hashimoto , Kyoko Egashira
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/105 , H01L27/10894 , H01L27/10897
摘要： A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.
摘要翻译：存储单元晶体管和平面电容器设置在存储区域中，CMOS器件的两个晶体管都设置在逻辑电路区域中。平面电容器的电容电介质15和平板电极16b设置在与浅沟槽隔离层12a共同的沟槽上，并且沟槽的上部填充有电容电介质15和板电极16b。形成作为存储节点的n型扩散层19，其端部区域沿着沟槽的上部的一侧延伸到与浅沟槽隔离层12a重叠的区域。可以增加用作电容器的基板的一部分的面积，而不增加基板面积。

5. 发明授权

US5300814A Semiconductor device having a semiconductor substrate with reduced step between memory cells 失效
标题翻译：半导体器件具有在存储单元之间具有减小的步骤的半导体衬底
公开(公告)号：US5300814A
公开(公告)日：1994-04-05
申请号：US915898
申请日：1992-07-17
申请人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
发明人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/10 , H01L27/105 , H01L27/108 , H01L23/48 , H01L29/46
CPC分类号： H01L27/105 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S257/92
摘要： A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.
摘要翻译：一种半导体器件，包括半导体衬底，多个存储单元区域，每个存储单元区域具有设置在半导体衬底上的多个存储单元，形成在半导体衬底上方的第一级中的字线，形成在第二级上方的位线第一级和背衬线，其具有比字线更低的电阻并且形成在高于第二级的第三级中。在存储单元区域外部的第二电平中形成虚拟位线，以便减小形成在存储单元区域周边的台阶。虚拟位线也用于互连字线和背衬线，使得它们之间的电连接稳定。

6. 发明授权

US08679955B2 Method for forming epitaxial wafer and method for fabricating semiconductor device 有权
标题翻译：用于形成外延晶片的方法和用于制造半导体器件的方法
公开(公告)号：US08679955B2
公开(公告)日：2014-03-25
申请号：US13202419
申请日：2010-02-10
申请人： Shin Hashimoto , Katsushi Akita , Kensaku Motoki , Hideaki Nakahata , Shinsuke Fujiwara
发明人： Shin Hashimoto , Katsushi Akita , Kensaku Motoki , Hideaki Nakahata , Shinsuke Fujiwara
IPC分类号： H01L21/20
CPC分类号： H01L21/0262 , C30B25/02 , C30B29/16 , C30B29/403 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L33/007
摘要： A method for forming an epitaxial wafer is provided as one enabling growth of a gallium nitride based semiconductor with good crystal quality on a gallium oxide region. In step S107, an AlN buffer layer 13 is grown. In step S108, at a time t5, a source gas G1 containing hydrogen, trimethylaluminum, and ammonia, in addition to nitrogen, is supplied into a growth reactor 10 to grow the AlN buffer layer 13 on a primary surface 11a. The AlN buffer layer 13 is so called a low-temperature buffer layer. After a start of film formation of the buffer layer 13, in step S109 supply of hydrogen (H2) is started at a time t6. At the time t6, H2, N2, TMA, and NH3 are supplied into the growth reactor 10. A supply amount of hydrogen is increased between times t6 and t7, and at the time t7 the increase of hydrogen is terminated to supply a constant amount of hydrogen. At the time t7, H2, TMA, and NH3 are supplied into the growth reactor 10.
摘要翻译：提供了一种用于形成外延晶片的方法，其可以在氧化镓区域上使得能够以良好的晶体质量生长氮化镓基半导体。在步骤S107中，生长AlN缓冲层13。在步骤S108中，在时刻t5，将除了氮以外的氢，三甲基铝和氨的原料气G1供给到生长反应器10中，以在主面11a上生长AlN缓冲层13。 AlN缓冲层13被称为低温缓冲层。在开始形成缓冲层13之后，在步骤S109中，在时刻t6开始供给氢（H2）。在时间t6，H2，N2，TMA和NH3被供应到生长反应器10中。在时间t6和t7之间，氢的供应量增加，而在时间t7，氢的增加被终止以提供恒定的量的氢。在时间t7，将H2，TMA和NH3供应到生长反应器10中。

7. 发明授权

US08633514B2 Group III nitride semiconductor wafer and group III nitride semiconductor device 有权
标题翻译： III族氮化物半导体晶片和III族氮化物半导体器件
公开(公告)号：US08633514B2
公开(公告)日：2014-01-21
申请号：US13409798
申请日：2012-03-01
申请人： Shin Hashimoto , Tatsuya Tanabe , Katsushi Akita , Hideaki Nakahata , Hiroshi Amano
发明人： Shin Hashimoto , Tatsuya Tanabe , Katsushi Akita , Hideaki Nakahata , Hiroshi Amano
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L21/0262 , H01L21/02661 , H01L29/2003 , H01L29/66212 , H01L29/66462 , H01L29/872
摘要： A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0
摘要翻译：提供III族氮化物半导体器件和III族氮化物半导体晶片。 III族氮化物半导体器件具有包含含有Al的III族氮化物基半导体的沟道层。 III族氮化物半导体器件可以增强二维电子气的迁移率并改善电流特性。 III族氮化物半导体晶片用于制造III族氮化物半导体器件。 III族氮化物半导体晶片包括由AlXGa1-XN（0

8. 发明申请

US20120211801A1 GROUP III NITRIDE LAMINATED SEMICONDUCTOR WAFER AND GROUP III NITRIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：第III组氮化物层叠半导体晶体管和III族氮化物半导体器件
公开(公告)号：US20120211801A1
公开(公告)日：2012-08-23
申请号：US13392998
申请日：2010-08-23
申请人： Shin Hashimoto , Katsushi Akita , Hideaki Nakahata , Hiroshi Amano
发明人： Shin Hashimoto , Katsushi Akita , Hideaki Nakahata , Hiroshi Amano
IPC分类号： H01L29/778 , H01L29/205
CPC分类号： H01L29/7785 , H01L29/2003
摘要： There is provided a normally-off group III nitride semiconductor device having a high breakdown field strength and minimal crystal defects, and a group III nitride laminated semiconductor wafer used to make the group III nitride semiconductor device. The group III nitride laminated semiconductor wafer 10 includes a substrate 27 which is made of AlN and has a main surface 27a along the c-axis of the AlN crystal, a first AlX1InY1Ga1-X1-Y1N layer 13 which is made of a group III nitride-based semiconductor containing Al and is provided on the main surface 27a, and a second AlX2InY2Ga1-X2-Y2N layer 15 which is provided on the main surface 27a, is made of a group III nitride-based semiconductor having a larger bandgap than the first AlX1InY1Ga1-X1-Y1N layer 13, and forms a heterojunction with the first AlX1InY1Ga1-X1-Y1N layer 13.
摘要翻译：提供了具有高击穿场强度和最小晶体缺陷的常规III族氮化物半导体器件，以及用于制造III族氮化物半导体器件的III族氮化物层压半导体晶片。 III族氮化物层叠半导体晶片10包括由AlN制成并具有沿AlN晶体的c轴的主表面27a的基板27，由III族氮化物制成的第一AlX1InY1Ga1-X1-Y1N层13 包含Al并且设置在主表面27a上，并且设置在主表面27a上的第二AlX2InY2Ga1-X2-Y2N层15由具有比第一个更大的带隙的III族氮化物基半导体制成 AlX1InY1Ga1-X1-Y1N层13，与第一AlX1InY1Ga1-X1-Y1N层13形成异质结。

9. 发明申请

US20120070929A1 METHOD FOR FABRICATING WAFER PRODUCT AND METHOD FOR FABRICATING GALLIUM NITRIDE BASED SEMICONDUCTOR OPTICAL DEVICE 有权
标题翻译：用于制造波形产品的方法和用于制造基于氮化镓的半导体光学器件的方法
公开(公告)号：US20120070929A1
公开(公告)日：2012-03-22
申请号：US13318039
申请日：2010-03-01
申请人： Shin Hashimoto , Katsushi Akita , Kensaku Motoki , Shinsuke Fujiwara , Hideaki Nakahata
发明人： Shin Hashimoto , Katsushi Akita , Kensaku Motoki , Shinsuke Fujiwara , Hideaki Nakahata
IPC分类号： H01L33/36 , H01L21/20
CPC分类号： C23C16/0227 , C23C16/0272 , C23C16/303 , C30B25/183 , C30B29/406 , H01L33/007
摘要： Provided is a method for fabricating a wafer product including an active layer grown on a gallium oxide substrate and allowing an improvement in emission intensity. In step S105, a buffer layer 13 comprised of a Group III nitride such as GaN, AlGaN, or AlN is grown at 600 Celsius degrees on a primary surface 11a of a gallium oxide substrate 11. After the growth of the buffer layer 13, while supplying a gas G2, which contains hydrogen and nitrogen, into a growth reactor 10, the gallium oxide substrate 11 and the buffer layer 13 are exposed to an atmosphere in the growth reactor 11 at 1050 Celsius degrees. A Group III nitride semiconductor layer 15 is grown on the modified buffer layer. The modified buffer layer includes, for example, voids. The Group III nitride semiconductor layer 15 can be comprised of GaN and AlGaN. When the Group III nitride semiconductor layer 15 is formed of these materials, excellent crystal quality is obtained on the modified buffer layer 14.
摘要翻译：本发明提供一种制造晶片产品的方法，该晶片产品包括在氧化镓衬底上生长的有源层并且能够提高发光强度。在步骤S105中，在氧化镓衬底11的主表面11a上以600摄氏度生长由诸如GaN，AlGaN或AlN的III族氮化物构成的缓冲层13.在缓冲层13生长之后，同时将含有氢和氮的气体G2供给到生长反应器10中，将氧化镓衬底11和缓冲层13在生长反应器11中的气氛中以1050摄氏度暴露。在改性缓冲层上生长III族氮化物半导体层15。改性缓冲层包括例如空隙。 III族氮化物半导体层15可以由GaN和AlGaN构成。当由这些材料形成III族氮化物半导体层15时，在改性缓冲层14上获得优异的晶体质量。

10. 发明授权

US07943964B2 AlxGayIn1−x−yN crystal substrate, semiconductor device, and method of manufacturing the same 有权
标题翻译： AlxGayIn1-x-yN晶体基板，半导体器件及其制造方法
公开(公告)号：US07943964B2
公开(公告)日：2011-05-17
申请号：US12096986
申请日：2006-10-16
申请人： Shinsuke Fujiwara , Tomoki Uemura , Takuji Okahisa , Koji Uematsu , Manabu Okui , Muneyuki Nishioka , Shin Hashimoto
发明人： Shinsuke Fujiwara , Tomoki Uemura , Takuji Okahisa , Koji Uematsu , Manabu Okui , Muneyuki Nishioka , Shin Hashimoto
IPC分类号： H01L33/30
CPC分类号： H01L21/02658 , C30B25/02 , C30B29/403 , H01L21/02389 , H01L21/0254
摘要： An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm−2 and at most 1×106 cm−2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.
摘要翻译：本发明的Al x Ga y In 1-x-y N晶体基板具有面积为至少10cm 2的主平面。主平面具有位于与主平面的外周5mm以内的外部区域和与外部区域以外的区域对应的内部区域。内部区域的总位错密度为1×102cm 2以上且1×10 6 cm -2以下。由此，可以提供具有大尺寸和合适的位错密度的Al x Ga y In 1-x-y N晶体基板，用作半导体器件的基板，包括Al x Ga y In 1-x-y N晶体基板的半导体器件，以及制造相同。

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