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1. 发明授权

US5300814A Semiconductor device having a semiconductor substrate with reduced step between memory cells 失效
标题翻译：半导体器件具有在存储单元之间具有减小的步骤的半导体衬底
公开(公告)号：US5300814A
公开(公告)日：1994-04-05
申请号：US915898
申请日：1992-07-17
申请人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
发明人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/10 , H01L27/105 , H01L27/108 , H01L23/48 , H01L29/46
CPC分类号： H01L27/105 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S257/92
摘要： A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.
摘要翻译：一种半导体器件，包括半导体衬底，多个存储单元区域，每个存储单元区域具有设置在半导体衬底上的多个存储单元，形成在半导体衬底上方的第一级中的字线，形成在第二级上方的位线第一级和背衬线，其具有比字线更低的电阻并且形成在高于第二级的第三级中。在存储单元区域外部的第二电平中形成虚拟位线，以便减小形成在存储单元区域周边的台阶。虚拟位线也用于互连字线和背衬线，使得它们之间的电连接稳定。

2. 发明授权

US5983331A Semiconductor integrated circuit having a plurality of chips 失效
标题翻译：具有多个芯片的半导体集成电路
公开(公告)号：US5983331A
公开(公告)日：1999-11-09
申请号：US943411
申请日：1997-09-30
申请人： Hironori Akamatsu , Toshio Yamada , Hisakazu Kotani , Yoshiro Nakata
发明人： Hironori Akamatsu , Toshio Yamada , Hisakazu Kotani , Yoshiro Nakata
IPC分类号： G06F15/78 , G11C11/401 , G06F12/00
CPC分类号： G06F15/7832
摘要： A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.
摘要翻译：作为母芯片的CPU与作为辅助芯片的DRAM组合安装。模式输出电路能够设置DRAM的存储容量以及用于通过DRAM的模式输出端和CPU的模式输入端转发到CPU的模式输入电路的DRAM的刷新周期。 CPU根据来自模式输入电路的数据控制地址生成器，根据DRAM存储容量和DRAM刷新周期设定用于存取DRAM的地址数据的位数。

3. 发明授权

US6005401A Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method 失效
标题翻译：用于连接半导体晶片和探针端子的IC端子的半导体晶片封装，方法和装置，半导体集成电路的测试方法，探针卡及其制造方法
公开(公告)号：US6005401A
公开(公告)日：1999-12-21
申请号：US837954
申请日：1997-04-14
申请人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
发明人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2886 , G01R1/0491 , G01R31/2867 , G01R31/2831
摘要： A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
摘要翻译：提供了一种保持板，其具有多个用于测试半导体芯片的集成电路端子的半导体晶片，与具有电连接到其相应的集成电路端子的多个探针端子的探针片相对。具有与多个探针端子电连接的布线的绝缘基板设置在与保持板相对的探针片上。在探针片和绝缘基片之间插入弹性部件。保持板和探针片的关系使得由保持板保持的半导体晶片的每个集成电路端子电连接到其对应的探针片的探针端子。

4. 发明授权

US06323663B1 Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method 有权
标题翻译：用于连接半导体晶片和探针端子的IC端子的半导体晶片封装，方法和装置，半导体集成电路的测试方法，探针卡及其制造方法
公开(公告)号：US06323663B1
公开(公告)日：2001-11-27
申请号：US09396884
申请日：1999-09-16
申请人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
发明人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
IPC分类号： G01R1073
CPC分类号： G01R31/2886 , G01R1/0491 , G01R31/2831 , G01R31/2867
摘要： A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
摘要翻译：提供了一种保持板，其具有多个用于测试半导体芯片的集成电路端子的半导体晶片，与具有电连接到其相应的集成电路端子的多个探针端子的探针片相对。具有与多个探针端子电连接的布线的绝缘基板设置在与保持板相对的探针片上。在探针片和绝缘基片之间插入弹性部件。保持板和探针片的关系使得由保持板保持的半导体晶片的每个集成电路端子电连接到其对应的探针片的探针端子。

5. 发明授权

US5945834A Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method 失效
公开(公告)号：US5945834A
公开(公告)日：1999-08-31
申请号：US609150
申请日：1996-02-29
申请人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
发明人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2886 , G01R1/0491 , G01R31/2867 , G01R31/2831
摘要： A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

6. 发明申请

US20120268167A1 Semiconductor Device and Method of Controlling the Same 审中-公开
标题翻译：半导体器件及其控制方法
公开(公告)号：US20120268167A1
公开(公告)日：2012-10-25
申请号：US13540198
申请日：2012-07-02
申请人： Toshio Yamada , Kazuo Tanaka , Akinobu Watanabe , Shigeru Yamamoto , Yukio Hiraiwa
发明人： Toshio Yamada , Kazuo Tanaka , Akinobu Watanabe , Shigeru Yamamoto , Yukio Hiraiwa
IPC分类号： H03K19/094
CPC分类号： H03K3/356165 , H03K3/012 , H03K3/356182 , H03K19/018507
摘要： A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.
摘要翻译：如果在上拉电路（总线保持电路）的电源电压和输入端子之间发生电位差，则上拉电路防止产生泄漏电流。总线保持电路中设置有控制端子。输入端子和控制端子的输入被输入到或非门，并且NOR门的输出被输入到控制输入端子和总线保持电源电压之间的耦合的第一MOSFET的栅极端子电路。提供第二个MOSFET（控制MOSFET）作为由控制端子的反相输出操作的开关。通过串联耦合第一个MOSFET和控制MOSFET，可以以更高的精度控制输入端子和电源电压之间的耦合，从而防止漏电流的产生。

7. 发明授权

US07858168B2 Honeycomb structure and manufacturing method of the same 有权
标题翻译：蜂窝结构和制造方法相同
公开(公告)号：US07858168B2
公开(公告)日：2010-12-28
申请号：US12410796
申请日：2009-03-25
申请人： Toshio Yamada , Takeshi Tokunaga , Makoto Furutani
发明人： Toshio Yamada , Takeshi Tokunaga , Makoto Furutani
IPC分类号： B32B3/12
CPC分类号： B01D46/247 , B01D46/2418 , B01D46/2451 , B01D46/2459 , B01D46/2466 , B01D46/2474 , B01D2046/2481 , B01D2046/2485 , B01D2046/2488 , B01D2046/2496 , B01D2279/30 , B28B11/006 , B28B11/007 , F01N3/2828 , F01N2330/06 , F01N2330/32 , F01N2330/48 , Y10T428/24149 , Y10T428/24157 , Y10T428/24165
摘要： There is disclosed a honeycomb structure in which while sufficiently maintaining a collection efficiency and a bonding strength of a plugging portion, a thermal shock resistance is improved. A plugging portion 32 is formed in the end of each cell 3 of a honeycomb structure 1, and a gap 34 having a size of 20 μm or more is formed between the plugging portion 32 and each partition wall 2. Moreover, the length of the gap 34 in the axial direction is 50% or more and less than 95% of the length of the plugging portion 32 in the axial direction, the length of the gap in a face vertical to the axial direction is 20% or more and 50% or less of the length of the inner peripheral surface of the cell 3, and the gaps are formed in at least ⅓ of the plugging portions 32.
摘要翻译：公开了一种蜂窝结构体，其中，尽管充分保持了封堵部分的收集效率和接合强度，但是耐热冲击性得到改善。在蜂窝结构体1的每个电池单元3的端部形成有堵塞部分32，并且在封堵部分32和每个分隔壁2之间形成尺寸为20μm或更大的间隙34。轴向的间隙34为堵塞部32的轴向长度的50％以上且小于95％，与轴方向垂直的面的间隙的长度为20％以上且50％以上，或更小的单元3的内周表面的长度，并且在至少1/3的封堵部分32中形成间隙。

8. 发明授权

US07645427B2 Honeycomb structure, manufacturing method of the structure, and exhaust gas purification system using the structure 有权
标题翻译：蜂窝结构，结构的制造方法和使用该结构的废气净化系统
公开(公告)号：US07645427B2
公开(公告)日：2010-01-12
申请号：US10667339
申请日：2003-09-23
申请人： Shogo Hirose , Toshio Yamada
发明人： Shogo Hirose , Toshio Yamada
IPC分类号： F01N3/022 , F01N3/023 , F01N3/24
CPC分类号： B01D46/247 , B01D46/0063 , B01D46/2451 , B01D46/2455 , B01D46/2466 , B01D46/2474 , B01D2046/2477 , B01D2046/2481 , B01D2046/2488 , B01D2046/2496 , B01J35/04 , F01N3/0222 , F01N2260/16 , F01N2330/06 , F01N2330/30 , Y02T10/20 , Y10S55/30 , Y10T29/49345
摘要： There is provided a honeycomb structure usable in a filter for trapping/collecting particulates included in exhaust gas and in which ashes deposited inside can be removed without requiring any special mechanism or apparatus or without detaching the filter from an exhaust system. The honeycomb structure includes: a plurality of through channels 9 separated by porous partition walls 7 and extending in the axial direction of the honeycomb structure; and plugging portions 11 for plugging one end of each of predetermined through channels 9a and an opposite end of each of the rest of through channels 9b in a checkered flag pattern, alternately. In the honeycomb structure, at least one slit 15 per through channel is formed in the vicinity of the plugging portions 11 of the partition walls 7 surrounding the respective through channels 9b.
摘要翻译：提供了一种可用于捕集/收集废气中所含的微粒的过滤器的蜂窝结构，其中可以除去内部沉积的灰烬，而不需要任何特殊的机构或装置，或者不将过滤器从排气系统分离。蜂窝结构体包括：多孔分隔壁7分隔开并沿蜂窝结构体的轴向延伸的多个通道9; 以及堵塞部分11，用于以预定的通道9a和其余贯通通道9b的每一个的相对端交替地插入方格标志图案。在蜂窝结构体中，在贯通通道9b的分隔壁7的封堵部11附近，形成有贯通通道的至少一个狭缝15。

9. 发明授权

US07486544B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07486544B2
公开(公告)日：2009-02-03
申请号：US11826636
申请日：2007-07-17
申请人： Ryo Mori , Toshio Yamada , Tetsuya Muraya
发明人： Ryo Mori , Toshio Yamada , Tetsuya Muraya
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/412
摘要： The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.
摘要翻译：本发明提供一种半导体集成电路器件，其具有泄漏电流降低的SRAM。在包括多个存储单元的SRAM中，每个存储单元由两个反相器电路的输入和输出端子交叉存储的存储器构成，以及设置在存储和互补位线之间并且其栅极连接到字线的选择MOSFET，提供了衬底偏置开关电路。在正常操作中，衬底偏置开关电路将电源电压提供给形成存储单元的P沟道MOSFET的N型阱，并将电路的接地电位提供给P型阱，其中，形成N沟道MOSFET。在待机状态下，衬底偏置开关电路提供低于电源电压的预定电压，并且N型阱和P沟道MOSFET的源极之间的PN结未被正向偏置到N 并且提供比地电位高的预定电压，并且P型阱和N沟道MOSFET的源极之间的PN结未被正向偏置到P型阱。

10. 发明申请

US20080258177A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20080258177A1
公开(公告)日：2008-10-23
申请号：US12102777
申请日：2008-04-14
申请人： Hiroyuki IKEDA , Toshio Sasaki , Akinobu Watanabe , Toshio Yamada , Akihisa Uchida
发明人： Hiroyuki IKEDA , Toshio Sasaki , Akinobu Watanabe , Toshio Yamada , Akihisa Uchida
IPC分类号： H01L27/088
CPC分类号： H01L27/11 , G11C5/14 , H01L27/0207
摘要： Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.
摘要翻译：连接到用于衬底偏置电路的从属开关电路单元的栅电极的布线分别电连接到用于电源电位的布线和用于参考电位的布线。因此，从开关电路单元的开关动作无效。连接到各个电路单元的n个阱的布线电连接到用于电源电位的布线，并且连接到各个电路单元的p阱的布线电连接到布线。因此，n个阱被固定到电源电位，并且p阱被固定到参考电位。

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