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1. 发明申请

US20070278662A1 Inspection apparatus and method for semiconductor IC 失效
标题翻译：半导体IC检测装置及方法
公开(公告)号：US20070278662A1
公开(公告)日：2007-12-06
申请号：US11806766
申请日：2007-06-04
申请人： Naomi Miyake , Yoshiro Nakata
发明人： Naomi Miyake , Yoshiro Nakata
IPC分类号： H01L23/12
CPC分类号： G01R31/2874 , G01R31/2879
摘要： The connection between a PTC element 22a corresponding to each semiconductor IC 11a and a power-supply line 25a is performed via a relay, a high voltage is supplied to the power-supply line 25a by sequentially turning on the relays, and a high voltage is supplied to each PTC element 22a in order, whereby it is possible to trip beforehand a PTC element 22a connected to a DC-defective semiconductor IC 11a. In this state, wafer level burn-in is performed together, which enables the PTC element 22a to be positively tripped during the burn-in for the DC defect of the semiconductor IC 11a, with the result that it is possible to increase the reliability of the burn-in.
摘要翻译：通过继电器执行对应于每个半导体IC11a的PTC元件22a与电源线路25a之间的连接，通过依次接通继电器将电压提供给电源线路25a，并且向每个PTC元件22a依次提供高电压，从而可以预先跳开连接到DC缺陷半导体IC11a的PTC元件22a。在这种状态下，一起进行晶片级老化，这使得PTC元件22a在半导体IC11a的DC缺陷的老化期间能够被正确地跳变，结果是可以增加老化的可靠性。

2. 发明授权

US06784681B2 Semiconductor integrated circuit testing system and method 有权
标题翻译：半导体集成电路测试系统及方法
公开(公告)号：US06784681B2
公开(公告)日：2004-08-31
申请号：US09964480
申请日：2001-09-28
申请人： Keiichi Fujimoto , Yoshiro Nakata
发明人： Keiichi Fujimoto , Yoshiro Nakata
IPC分类号： G01R3126
CPC分类号： G01R1/0735
摘要： A semiconductor integrated circuit testing system for testing electric characteristics of a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer in the lump includes a wafer tray for holding the semiconductor wafer and an interconnect substrate facing the semiconductor wafer held on the wafer tray and having interconnect layers to which a testing voltage is externally input. A ring-shaped sealing member is provided between the wafer tray and the interconnect substrate so as to form a sealed space together with the wafer tray and the interconnect substrate. An elastic sheet is held on the interconnect substrate at the periphery thereof. A plurality of probe terminals electrically connected to the interconnect layers are provided on the elastic sheet in positions respectively corresponding to external electrodes of the plural semiconductor integrated circuit devices. A plurality of protrusions protruding toward the wafer tray are provided on the elastic sheet for preventing the interconnect substrate from deforming toward the wafer tray when the internal pressure of the sealed space is reduced.
摘要翻译：用于测量形成在半导体晶片上的多个半导体集成电路器件的电特性的半导体集成电路测试系统包括用于保持半导体晶片的晶片托盘和面向保持在晶片托盘上的半导体晶片的互连基板，并且具有外部输入测试电压的互连层。在晶片托盘和互连基板之间设置环形密封件，以便与晶片托盘和互连基板一起形成密封空间。弹性片在其周边上保持在互连基板上。电连接到互连层的多个探针端子分别设置在弹性片上，分别对应于多个半导体集成电路器件的外部电极。在弹性片上设置有朝向晶片托盘突出的多个突起，用于防止当密封空间的内部压力降低时互连基板朝向晶片托盘变形。

3. 发明授权

US5983331A Semiconductor integrated circuit having a plurality of chips 失效
标题翻译：具有多个芯片的半导体集成电路
公开(公告)号：US5983331A
公开(公告)日：1999-11-09
申请号：US943411
申请日：1997-09-30
申请人： Hironori Akamatsu , Toshio Yamada , Hisakazu Kotani , Yoshiro Nakata
发明人： Hironori Akamatsu , Toshio Yamada , Hisakazu Kotani , Yoshiro Nakata
IPC分类号： G06F15/78 , G11C11/401 , G06F12/00
CPC分类号： G06F15/7832
摘要： A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.
摘要翻译：作为母芯片的CPU与作为辅助芯片的DRAM组合安装。模式输出电路能够设置DRAM的存储容量以及用于通过DRAM的模式输出端和CPU的模式输入端转发到CPU的模式输入电路的DRAM的刷新周期。 CPU根据来自模式输入电路的数据控制地址生成器，根据DRAM存储容量和DRAM刷新周期设定用于存取DRAM的地址数据的位数。

4. 发明授权

US5829126A Method of manufacturing probe card 失效
标题翻译：探针卡的制造方法
公开(公告)号：US5829126A
公开(公告)日：1998-11-03
申请号：US638038
申请日：1996-04-26
申请人： Koichi Nagao , Yoshiro Nakata , Shinichi Oki
发明人： Koichi Nagao , Yoshiro Nakata , Shinichi Oki
IPC分类号： G01R31/26 , G01R1/067 , G01R1/073 , G01R3/00 , H01L21/66 , H05K3/40 , H05K3/42 , H01R9/00
CPC分类号： G01R1/06738 , G01R1/06761 , G01R3/00 , H05K3/4007 , G01R1/07307 , H01R12/714 , H05K2201/0347 , H05K2201/0355 , H05K2201/0367 , H05K2201/0373 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0278 , H05K2203/1152 , H05K3/423 , Y10T29/49004 , Y10T29/49149
摘要： Bumps to be connected to inspection electrodes of semiconductor chips are formed on a surface of a flexible substrate. A plating layer is formed which is made of a harder material than the bumps formed on the flexible substrate and which has a concave portion or a convex portion whose diameter is equal to or smaller than half the diameter of the bumps, on a flat metallic plate. The plating layer of the metallic plate is pressed against top surfaces of the bumps, so that irregularities are formed in the top surfaces of the bumps.
摘要翻译：在柔性基板的表面上形成要连接到半导体芯片的检查电极的凸起。形成电镀层，该镀层比形成在柔性基板上的凸点更硬的材料制成，并且在平坦的金属板上具有直径等于或小于凸块的直径的一半的凹部或凸部。金属板的镀层被压在凸块的顶表面上，从而在凸块的顶表面上形成凹凸。

5. 发明授权

US5605844A Inspecting method for semiconductor devices 失效
标题翻译：半导体器件检测方法
公开(公告)号：US5605844A
公开(公告)日：1997-02-25
申请号：US624954
申请日：1996-03-27
申请人： Shinichi Oki , Koichi Nagao , Yoshiro Nakata
发明人： Shinichi Oki , Koichi Nagao , Yoshiro Nakata
IPC分类号： G01R31/28 , H01L21/68 , H01L21/66
CPC分类号： G01R31/287 , G01R31/2884 , H01L21/6835 , H01L21/6836 , G01R31/2831 , H01L2221/68322 , H01L2221/68327 , H01L2224/16
摘要： A semiconductor wafer is affixed on a dicing sheet having an appropriate expansibility. Then, a dicing operation is performed on the semiconductor wafer without dividing the dicing sheet, thereby dividing a plurality of semiconductor chips from each other. After aligning a contactor against the semiconductor wafer, the semiconductor wafer is fixed to the contactor. In this case, protrusions provided on the contactor are inserted into the gap between semiconductor chips. The protrusions cause a shift movement toward the peripheral edge of the contactor in response to thermal expansion of the contactor, thereby expanding the gap between semiconductor chips. Then a burn-in is performed on all of the plural semiconductor chips of which gap is expanded.
摘要翻译：将半导体晶片固定在具有适当膨胀性的切割片上。然后，在半导体晶片上进行切割操作，而不分割切割片，从而将多个半导体芯片彼此分开。在将接触器对准半导体晶片之后，将半导体晶片固定到接触器。在这种情况下，设置在接触器上的突起插入到半导体芯片之间的间隙中。这些突起响应于接触器的热膨胀而导致朝向接触器的周缘移动移动，从而扩大了半导体芯片之间的间隙。然后在其间隙扩大的所有多个半导体芯片上进行老化。

6. 发明授权

US5399890A Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level 失效
标题翻译：半导体存储器件，其中存储单元的电容器电极和外围电路的互连层形成在一个级中
公开(公告)号：US5399890A
公开(公告)日：1995-03-21
申请号：US257955
申请日：1994-06-10
申请人： Shozo Okada , Hisashi Ogawa , Naoto Matsuo , Yoshiro Nakata , Toshiki Yabu , Susumu Matsumoto
发明人： Shozo Okada , Hisashi Ogawa , Naoto Matsuo , Yoshiro Nakata , Toshiki Yabu , Susumu Matsumoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.
摘要翻译：本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个位于层叠电容器和第一级互连层之上的第二级互连层。多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。第二电极层连接到多个第二级互连层之一的一部分。多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。

7. 发明授权

US5355081A Method for testing a semiconductor integrated circuit having self testing circuit 失效
标题翻译：用于测试具有自检电路的半导体集成电路的方法
公开(公告)号：US5355081A
公开(公告)日：1994-10-11
申请号：US65123
申请日：1993-05-20
申请人： Yoshiro Nakata , Atsushi Fujiwara , Akinori Shibayama
发明人： Yoshiro Nakata , Atsushi Fujiwara , Akinori Shibayama
IPC分类号： H01L27/10 , G01R31/28 , H01L21/66 , G01R15/12
CPC分类号： G01R31/2884
摘要： A method is provided for testing a semiconductor integrated circuit including a main circuit, a self testing circuit for testing at least one part of the functions of the main circuit, and a test result output circuit having at least one light emitting device for outputting results from the self testing circuit in the form of light. The method includes the steps of inputting a test start to the self testing circuit so as to initiate operation of the self testing circuit; detecting light emitted from the light emitting device with an optical system, the light being emitted based on the test results from the self testing circuit; and obtaining the test results based on the light detection.
摘要翻译：提供了一种用于测试半导体集成电路的方法，该半导体集成电路包括主电路，用于测试主电路功能的至少一部分的自检电路，以及具有至少一个发光装置的测试结果输出电路，自检电路以光的形式。该方法包括以下步骤：将测试开始输入到自检电路，以启动自检电路的操作; 利用光学系统检测从发光装置发出的光，基于来自自检电路的测试结果发射光; 并基于光检测获得测试结果。

8. 发明授权

US5300814A Semiconductor device having a semiconductor substrate with reduced step between memory cells 失效
标题翻译：半导体器件具有在存储单元之间具有减小的步骤的半导体衬底
公开(公告)号：US5300814A
公开(公告)日：1994-04-05
申请号：US915898
申请日：1992-07-17
申请人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
发明人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/10 , H01L27/105 , H01L27/108 , H01L23/48 , H01L29/46
CPC分类号： H01L27/105 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S257/92
摘要： A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.
摘要翻译：一种半导体器件，包括半导体衬底，多个存储单元区域，每个存储单元区域具有设置在半导体衬底上的多个存储单元，形成在半导体衬底上方的第一级中的字线，形成在第二级上方的位线第一级和背衬线，其具有比字线更低的电阻并且形成在高于第二级的第三级中。在存储单元区域外部的第二电平中形成虚拟位线，以便减小形成在存储单元区域周边的台阶。虚拟位线也用于互连字线和背衬线，使得它们之间的电连接稳定。

9. 发明授权

US5217914A Method for making semiconductor integration circuit with stacked capacitor cells 失效
标题翻译：具有层叠电容器单元的半导体积分电路的方法
公开(公告)号：US5217914A
公开(公告)日：1993-06-08
申请号：US683603
申请日：1991-04-10
申请人： Susumu Matsumoto , Toshiki Yabu , Yoshiro Nakata , Naoto Matsuo , Shozo Okada , Hiroyuki Sakai
发明人： Susumu Matsumoto , Toshiki Yabu , Yoshiro Nakata , Naoto Matsuo , Shozo Okada , Hiroyuki Sakai
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/91
摘要： Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.
摘要翻译：公开了具有层叠电容器单元的半导体积分电路。每个单元包括用于存储电荷的电荷存储电极，以及集成在其上的电容器绝缘膜和相对的平板电极。电荷存储电极基本上由至少双框状部分或至少一个柱状部分中的底部和部分组成，以及围绕从底面向上升起的柱状部分的至少一个框状部分。电容器沉积膜由沉积在电荷存储电极的所有底面和所有表面上的介电材料膜构成，并与相对的板电极配合构建电容器。所述制造叠层电容器电池的方法可以通过重复氧化膜和导电膜的沉积以及各向异性蚀刻来形成自对准电容器。

10. 发明授权

US06781400B2 Method of testing semiconductor integrated circuits and testing board for use therein 有权
标题翻译：半导体集成电路测试方法及其中使用的测试板
公开(公告)号：US06781400B2
公开(公告)日：2004-08-24
申请号：US10322571
申请日：2002-12-19
申请人： Yoshiro Nakata , Shinichi Oki
发明人： Yoshiro Nakata , Shinichi Oki
IPC分类号： G01R3102
CPC分类号： G01R31/2886
摘要： A method of testing semiconductor integrated circuits comprises the step of simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to the respective testing electrodes of the semiconductor integrated circuit elements. The simultaneous testing step includes the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via PTC elements provided for the semiconductor integrated circuit elements in a one-to-one relationship.
摘要翻译：一种测试半导体集成电路的方法包括通过向半导体集成电路元件的各个测试电极施加电压来同时测试用于电特性的多个半导体集成电路元件的步骤。同时测试步骤包括以一对一的关系将电压施加到半导体集成电路元件的各个测试电极的PTC元件。

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