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    • 6. 发明授权
    • Controlling method and apparatus for examination of multiport RAM(s)
    • 多端口RAM的检查方法和装置
    • US5812559A
    • 1998-09-22
    • US949705
    • 1992-09-23
    • Hiroshi NakaideFumihiko SaitoShinzi HiyamaKoji Ikuta
    • Hiroshi NakaideFumihiko SaitoShinzi HiyamaKoji Ikuta
    • G06F12/16G11C29/00G11C29/48G11C29/56
    • G11C29/48G11C8/16
    • A control method and apparatus for the examination of multiport RAM(s) connected between a CPU on a CPU side and a hardware circuit on a hardware circuit side. The method and apparatus are for use in a device comprising a single RAM or more. For instance, the device may have a first RAM and a second RAM having ports on CPU and a hardware circuit side of the RAMs. Each one port on the CPU side is connected to a CPU. The method and apparatus examine the ports on the hardware circuit as well as the CPU side ports. The method may comprise steps of reading data stored in the first RAM from a port on the hardware circuit of the first RAM and writing the data in the second RAM from the port on the hardware circuit side of the second RAM using a RAM examination controller. The data read from the one port of the first RAM on the CPU side of the RAMs is compared with the data from the other port of the second RAM on the CPU side of the RAMs. The operation of ports of the first RAM and the second RAM on the hardware circuit side of the RAMs is examined.
    • 一种用于检查连接在CPU侧的CPU与硬件电路侧的硬件电路之间的多端口RAM的控制方法和装置。 该方法和装置用于包括单个RAM或更多的设备。 例如,该设备可以具有第一RAM和第二RAM,其具有CPU上的端口和RAM的硬件电路侧。 CPU侧的每个端口都连接到CPU。 该方法和装置检查硬件电路以及CPU侧端口上的端口。 该方法可以包括从第一RAM的硬件电路上的端口读取存储在第一RAM中的数据的步骤,并使用RAM检查控制器从第二RAM的硬件电路侧的端口写入第二RAM中的数据。 从RAM的CPU侧的第一RAM的一个端口读取的数据与来自RAM的CPU侧的第二RAM的另一个端口的数据进行比较。 检查RAM的硬件电路侧的第一RAM和第二RAM的端口的操作。